FIR chip for use in a wireless subscriber unit

A wireless subscriber unit includes a processor for transcoding an input signal to provide digital input symbols for demodulating a received output signal and from synthesizing digital output symbols from the demodulated output signal, the subscriber unit comprising a FIR chip including;

• an external address decoder means for internal address decoding connected to the processor, to allow the processor to access the internal functions of the FIR chip;
• a FIR filter for FIR filtering, connected to the processor to control the FIR filter;
• a transmit timer for control timing which allows the processor to control FIR filter;
• a receive timer for generating timing signals for timing transcoding operations and synthesizing operations in the processor;
• a control and status register, connected to the processor, which allows the processor to read the status of and control the internal functions of the integrated circuit;
• a ringer control connected to the control and status registers, said ringer control allows the processor to control a ringer circuit of the subscriber unit;
• a watchdog timer circuit, connected to the control and status register, for resetting said processor;
• a sample buffer for buffering received data samples before the data samples are output to the processing means;
• a fanout buffer for receiving a master clock signal from the subscriber unit for buffering the master clock signal before being input to a CODEC timer;
• an external address decoder, connected to the processor which allows the processor to access the remaining components of a subscriber unit.