Self-configuring distributed switch

A self-configuring switch, comprising:

• a memoryless channel switch for performing channel switching according to a predetermined time schedule;
• a global controller, the global controller including a global time counter circuit and a channel assignment mechanism, the channel assignment mechanism computing a predetermined time schedule for the memoryless channel switch;
• and
• a plurality of data switch modules connected to local data traffic sources through incoming links and to local data traffic sinks through outgoing links, and connected to the channel switch by a plurality of outgoing channels and a plurality of incoming channels, each module having a local controller and a local time counter circuit, means for sorting data units into data groups corresponding to the respective channels, a memory for storing the sorted data groups, means for determining a volume of data in each data group, means for reporting each volume of data to the global controller, means for receiving control signals from the global controller, and means for timing the transfer of sorted data from the data groups in accordance with the control signals.

An optical channel switch, comprising:

• an integer G>1 groups of incoming wavelength multiplexes each group including an integer n>1 of multiplexes, and each multiplex supporting an integer W>1 of optical wavelength channels;
• the integer G groups of wavelength demultiplexers, each demultiplexer being associated with an incoming multiplex;
• the integer G groups of optical space switches, each group including the integer W space switches, each space switch having n input and n output ports, the space switches being serially assigned numbers from 0 to (G×W−1), and a space switch assigned a number S being associated with wavelength number [S+G] modulo W
• the integer G groups of wavelength multiplexers, each multiplexer being associated with an outgoing multiplex;
• and
• the integer G groups of outgoing multiplexes, each group including n multiplexes, and each multiplex having W channels;
• whereby the incoming multiplexes, the space switches, and the outgoing multiplexes are connected such that:
• an mth input port of each n×n space switch S, the space switch being associated with a wavelength Λ, 0≦m<n, 0≦S<G×W, and 0≦Λ<W, is connected to a channel in the mth incoming multiplex belonging to a group [S/G] modulo G, the channel corresponding to wavelength Λ;
• and
• the mth output port of each n×n space switch S, 0≦m<n and 0≦S<G×W being connected to a channel corresponding to wavelength Λ in the mth outgoing multiplex belonging to an outgoing multiplex group, the group number being determined as the integer part of the ratio (S/W).

A method of timing coordination in a distributed switch comprising a plurality of data switching modules interconnected by a channel switch, a global switch controller being collocated with the channel switch and having negligible transmission delay to and from the channel switch, the global controller including a global time counter, each module having a local time counter, propagation delays from the modules to the global controller being generally unequal, the method comprising steps of:

• sending a timing packet from each of the modules to the global controller when the local cyclic time counter of a respective module is zero;
• attaching a time indication of the global time counter to the timing packet upon receiving the timing packet at the global controller, the time indication corresponding to a global time counter indication on receipt of a first bit of the timing packet;
• placing the timing packets in a transmit queue at the global controller;
• sending the timing packets back to the respective modules;
• and
• resetting the local time counters of the respective modules according to information extracted from the respective timing packets.

A mechanism for enabling an interleaving of delay-sensitive type-1 and delay-tolerant type-2 packets on a shared channel in a communication module having a local time counter C bits, the module transmitting type-1 and type-2 data packet streams on a shared channel, the mechanism comprising:

• a type-1 packet buffer;
• a type-2 packet buffer;
• a register for storing a transfer duration of a packet waiting in the type-2 packet buffer, the transfer duration being represented by an integer X≧0;
• an integer value produced from the output of a time counter;
• a comparator for comparing the values of the time counter and the transfer duration and producing a two-bit output Q, the output Q being “00” if transfer duration is smaller than the integer value of the time counter, and “11” if the integer value of the time counter zero, regardless of the value of the transfer duration;
• and
• a 2:1 selector for selecting a packet from the type-1 packet register if Q is “11”, the type-2 packet register if Q is “10”, and remaining in an idle state if Q is “00”.

A method of reconfiguring a channel switch having a global controller, N incoming multiplexes and N outgoing multiplexes connecting N data switching modules, comprising:

• storing available outgoing and incoming capacity of each data switching module in a 2×N module-state matrix;
• identifying the source module, the sink module, and the required capacity of each connection request;
• communicating the identifiers of each connection request to the global controller;
• the global controller tentatively accepting the request if the required capacity does not exceed the available outgoing capacity of the source module or the available incoming capacity of the sink module;
• the global controller storing the identifiers of connection requests in a connection-request queue if the request is tentatively accepted;
• the global controller storing the identifiers of connection requests in a standby queue if the request is not accepted;
• periodically sorting the entries of the request queue and the entries of the standby queue, if any, in a descending order according to the capacity requirements of the queued requests;
• periodically performing a matching process to assign each request in the request queue to a direct path;
• if a direct path is not found, performing a double-matching process to assign each request that cannot be routed in a direct path to a loop path;
• placing the identifiers of a successfully assigned connection in a progress queue;
• retaining the identifiers of unassigned connection requests for a subsequent assignment cycle;
• if any request in the request queue is not assigned to a path, repeating the matching process using the standby queue instead of the connection request queue;
• modifying the entries in the 2×N module-state matrix following each of the assignment decisions above;
• and
• communicating the assignment results to modules.