System and method for sequential testing of high speed serial link core

Abstract

A testing circuit in a serialization and deserialization (SerDes) core having a plurality of transmitter links and receiver links is provided for testing a series of at least three alternating transmitter and receiver links. The testing circuit includes a built-in-self-test (BIST) macro for generating test data and transmitting the test data to a first link of the series of transmitter and receiver links, and for receiving processed test data from a last link of the series of transmitter receiver links; and at least one test transmission line for transmitting test data received by a link of the series of transmitter and receiver links to a next link of the series of transmitter and receiver links, wherein the at least one test transmission line connects the at least three transmitter receiver links. Furthermore, a method is provided for testing a series of links having at least three alternating transmitter and receiver links of a plurality of transmitter and receiver links in a SerDes core. The method includes the steps of generating at least one test data signal; transmitting the at least one test data signal sequentially through the transmitter and receiver links of the series of links; receiving the at least one test data signal from a last link of the series of transmitter and receiver links; and checking the at least one test data signal received from the last link of the series of transmitter and receiver link for error.

Dependencies are inferred from the claim text.