US 2003/0189869 A1 · Semiconductor integrated circuit device having hierarchical power source arrangement

Abstract

A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of, an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

Claims73

Dependent claims

A semiconductor device receiving at an input node a signal which attains to a low level in a standby cycle and to a high level in an active cycle, said active cycle having a set period in which said signal changes from the low level to the high level, and a holding period in which said signal is maintained at the high level, said semiconductor device comprising:

a first power supply node receiving a voltage corresponding to said high level;
a first main power supply line coupled to said first power supply node for transmitting the voltage applied to said first power supply node;
a first subpower supply line;
first resistance means connected between said first main power supply line and said first subpower supply line;
first switching means connected between said first main power supply line and said first subpower supply line, which is rendered conductive in said stand-by cycle and said set period, and rendered non-conductive in said holding period;
a second power supply node receiving a voltage corresponding to said low level;
a second main power supply line transmitting the voltage applied to said second power supply node;
a second subpower supply line;
second resistance means connecting said second main power supply line and said second subpower supply line;
second switching means connected between said second main power supply line and said second subpower supply line, which is rendered non-conductive in said stand-by cycle and rendered conductive in said active cycle;
and
a logic gate operating using the voltage on said first main power supply line and the voltage on said second subpower supply line as operating power supply voltages for performing a predetermined logical operation on the signal at said input node.

9 more elements

A semiconductor device receiving at an input node a signal which attains to a high level in a stand-by cycle and to a low level in an active cycle, said active cycle having a set period in which said signal changes from the high level to the low level and a holding period in which said signal is maintained at the low level, said semiconductor device comprising:

a first power supply node receiving a voltage corresponding to said high level;
a first main power supply line coupled to said first power supply node for transmitting the voltage applied to said first power supply node;
a first subpower supply line;
first resistance means connecting said first main power supply line and said first subpower supply line;
first switching means connected between said first main power supply line and said first subpower supply line and rendered non-conductive in said stand-by cycle and conductive in said active cycle;
a second power supply node receiving a voltage corresponding to said low level;
a second main power supply line connected to said second power supply node for transmitting the voltage applied to said second power supply node;
a second subpower supply line;
second resistance means connecting said second main power supply line and said second subpower supply line;
second switching means connected between said second main power supply line and said second subpower supply line, and rendered conductive in said stand-by cycle and said set period, and non-conductive in said holding period;
and
a logic gate operating using the voltage on said first subpower supply line and the voltage on said second main power supply line as operating power supply voltages, for performing a prescribed logic processing on the signal applied to said input node.

9 more elements

A semiconductor device including a logic gate outputting a signal which attains to a first logic level in a stand-by cycle and to a second logic level in an active cycle, said active cycle including a set period in which the logic level of said signal changes and a holding period in which said signal holds said second logic level, said semiconductor device comprising:

a first power supply line to which a voltage corresponding to said first logic level is supplied from a first power supply node, serving as one operating power supply line for said logic gate;
first variable impedance means connected between said first power supply node and said first power supply line;
a second power supply line to which a voltage corresponding to said second logic level is supplied from a second power supply node, serving as another operating power supply line of said logic gate;
second variable impedance means connected between said second power supply node and said second power supply line;
and
impedance changing means for setting said first variable impedance means to a low impedance state and said second variable impedance means to a high impedance state in said stand-by cycle, setting first and second variable impedances both to the low impedance state in said set period, and setting said first variable impedance means to the high impedance state and said second variable impedance means to the low impedance state in said holding period.

3 more elements