Back to results
US 2003/0189867 A1Published application
Distributed FIFO in synchronous memory
AssigneeMicron Technology, Inc.
InventorsFrankie Fariborz Roohparvar, Dean Nobunaga
Life of this patent
Estimating the term…
Abstract
A synchronous memory device includes a distributed FIFO buffer in a read path. Buffer stages of the FIFO are located at remote ends of an internal data bus. The time needed for loading the first FIFO stage is reduced and allows shorter clock cycle times for some memory read operations.
Claims19
A synchronous non-volatile memory device comprising:
- an array of memory cells arranged in columns;
- sense amplifier circuitry coupled to the columns of the array;
- a first FIFO buffer stage coupled to the sense amplifier circuitry;
- an internal communication line traversing the memory device;
- a driver circuit coupled between the first FIFO buffer stage and the internal communication line;
- and
- a second FIFO buffer stage located remotely from the first FIFO buffer stage and coupled to receive an output from the first FIFO buffer stage via the internal communication line.
4 more elements
A synchronous memory device comprising:
- a differential sense amplifier;
- a first pass circuit coupled to the differential sense amplifier;
- a first latch circuit coupled to the first pass circuitry;
- a second pass circuit coupled to the first latch circuit;
- a first FIFO buffer stage coupled to the second pass circuit;
- a data driver circuit coupled between the first FIFO buffer stage and an internal data line;
- a second latch circuit coupled to the internal data line remote from the data driver circuit;
- a third pass circuit coupled to the second latch circuit;
- a second FIFO buffer stage coupled to the third pass circuit;
- a fourth pass circuit coupled to the second latch circuit;
- and
- a third FIFO buffer stage coupled to the fourth pass circuit.
9 more elements
A method of operating a synchronous memory device comprising:
- initiating a read operation on a first clock cycle;
- sensing data stored in a memory cell during the first clock cycle;
- latching the sensed data during the first clock cycle;
- coupling the latched data to a first FIFO buffer stage during the first clock cycle;
- driving an output of the first FIFO buffer stage on an internal data line during a second subsequent clock cycle;
- and
- coupling the internal data line to a second FIFO buffer stage during the second clock cycle.
4 more elements
A method of operating a synchronous memory device comprising:
- initiating a read operation on a first clock cycle;
- sensing data stored in a memory cell during the first clock cycle;
- latching the sensed data during the first clock cycle;
- coupling the latched data to a first FIFO buffer stage during the first clock cycle;
- driving an output of the first FIFO buffer stage on an internal data line during a second subsequent clock cycle;
- coupling the internal data line to a second FIFO buffer stage during the second clock cycle;
- and
- driving data from the second FIFO buffer stage on an external data connection.
5 more elements
A method of operating a synchronous memory device comprising:
- initiating a read operation on a first clock cycle;
- sensing data stored in a memory cell during the first clock cycle;
- latching the sensed data during the first clock cycle;
- coupling the latched data to a first FIFO buffer stage during the first clock cycle;
- driving an output of the first FIFO buffer stage on an internal data line during the first clock cycle;
- coupling the internal data line to a second FIFO buffer stage during the first clock cycle;
- and
- coupling the second FIFO buffer stage to an output driver circuit during a second subsequent clock cycle.
5 more elements
Dependencies are inferred from the claim text.