Method and apparatus for determining digital delay line entry point
AssigneeMicron Technology, Inc.
InventorsTyler J. Gomm, Aaron M. Schoenfeld, Travis E. Dirkes, Ross E. Dermott
Life of this patent
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Abstract
A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.
Claims73
A system comprising:
- a processor;
- and
- a memory device coupled to the processor and comprising:
- a delay locked loop (DLL) circuit;
- and
- a counter coupled to the DLL circuit and configured to track an amount of delay in the DLL circuit.
A memory device comprising:
- a delay locked loop (DLL) circuit;
- and
- a counter coupled to the DLL circuit and configured to track an amount of added delay in the DLL circuit.
A system comprising:
- a processor;
- a memory device coupled to the processor and comprising a delay locked loop (DLL) circuit;
- and
- a counter coupled to the memory device and configured to track an amount of delay in the DLL circuit.
A method of tracking the entry point in a delay locked loop (DLL) circuit comprising the acts of:
- detecting a phase difference between a first signal and a second signal;
- producing an output comprising information corresponding to the phase difference between the first signal and the second signal;
- shifting an entry point in a delay line until the output corresponding to the phase difference indicates that the phase difference is essentially equal to zero, the entry point corresponding to a fixed number of delay elements in the delay line;
- and
- counting the number of delay elements associated with the entry point when the phase difference is essentially equal to zero.
A delay locked loop (DLL) circuit comprising:
- means for detecting a phase difference between a first signal and a second signal and for producing an output comprising information corresponding to the phase difference between the first signal and the second signal;
- means for shifting an entry point in a delay line until the output corresponding to the phase difference indicates that the phase difference is essentially equal to zero, the entry point corresponding to a fixed number of delay elements in the delay line;
- and
- means for counting the number of delay elements associated with the entry point when the phase difference is essentially equal to zero.
A memory device comprising:
- a delay locked loop (DLL) circuit;
- and
- a counter coupled to the DLL circuit.
A method of producing a plurality of memory devices comprising the acts of:
- electrically testing a portion of the plurality of memory devices, each of the memory devices comprising a delay locked loop (DLL) circuit;
- characterizing the DLL circuits based on the electrical testing of the portion of the plurality of memory devices;
- producing characterization data corresponding to a locking point of the DLL circuit;
- and
- redesigning the plurality of memory devices based on the characterization data.
Dependencies are inferred from the claim text.