Memory circuit

Abstract

The non-volatile memory cell of a memory circuit includes at least one enhancement pMOS transistor having a floating gate. It further includes an enhancement nMOS transistor having a floating gate insulated from the floating gate of the pMOS transistor. A control input is capacitively coupled to the floating gate of the pMOS transistor and to the floating gate of the nMOS transistor. The pMOS transistor and the nMOS transistor are connected by a connection point, the connection point being connected to an output of the memory cell. The pMOS transistor is additionally connected to a first terminal of the memory cell, while the nMOS transistor is additionally connected to a second terminal of the memory cell. A supply voltage is appliable to the memory cell via the first and second terminals.

Dependencies are inferred from the claim text.