Methods and devices for increasing voltages on non-selected wordlines during erasure of a flash memory
AssigneeSamsung Electronics Co., Ltd.
InventorSoung-Hoon Sim
Life of this patent
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Abstract
A flash memory can operate by providing a first voltage level from a row decoder to a wordline associated with a cell of a flash memory device. An address provided to the row decoder is decoded during an erase mode operation of the flash memory. The first voltage level is increased to a second voltage level provided from the row decoder to the wordline responsive to determining that the wordline is not selected by the address during the erase mode operation.
Claims22
A method of operating a row decoder of a flash memory comprising:
- providing a first voltage level from a row decoder to a wordline associated with a cell of a flash memory device;
- decoding an address provided to the row decoder during an erase mode operation of the flash memory;
- and
- increasing the first voltage level to a second voltage level provided from the row decoder to the wordline responsive to determining that the wordline is not selected by the address during the erase mode operation.
A method of operating a row decoder of a flash memory comprising increasing a pseudo-ground voltage to an output stage of a row decoder to increase a voltage applied to a non-selected wordline electrically coupled to the output stage.
A flash memory comprising:
- a split-gate memory cell having source and drain regions formed in a semiconductor substrate, a channel region between the source and drain regions, a floating gate partially covering the source and channel regions, and a control gate over the channel region and the floating gate;
- a wordline connected to the control gate;
- and
- a wordline decoder configured to supply a first voltage to the wordline when the wordline decoder is selected while to supply a second voltage to the wordline when the wordline is non-selected, in an erasure mode;
- wherein the wordline decoder comprises:
- first means configured to charge a node to a second voltage in response to a first signal delayed from an erasure signal during the non-selection;
- second means configured to charge the wordline to a second voltage in response to the node during the non-selection;
- a first transistor for connecting the wordline to the first voltage in response to the node;
- and a second transistor for connecting the node to the first voltage in response to the wordline.
A flash memory comprising:
- a split-gate memory cell having source and drain regions formed in a semiconductor substrate, a channel region between the source and drain regions, a floating gate partially covering the source and channel regions, and a control gate over the channel region and the floating gate;
- a wordline connected to the control gate;
- a bitline connected to the drain region;
- a source line connected to the source region;
- a node;
- a first transistor for connecting a first voltage to the wordline in response to the node;
- a second transistor for connecting the first voltage to the node in response to the wordline;
- a third transistor for connecting an address input terminal to the node in response to a first signal delayed from an erasure signal;
- a fourth transistor for connecting the address input terminal to the node in response to a second signal delayed from the erasure signal;
- and
- a fifth transistor for connecting the wordline to the second signal in response to the node.
A flash memory device comprising:
- a row decoder circuit configured to increase a first voltage level on a wordline during an erase mode operation to a second voltage level provided from the row decoder circuit to the wordline responsive to determining that the wordline is not selected by the address during the erase mode operation.
Dependencies are inferred from the claim text.