Timer circuit and semiconductor memory incorporating the timer circuit

(Amended) A semiconductor memory device having:

• memory cells dynamically storing data;
• and
• a timer circuit generating a signal which defines a refresh cycle of said memory cells,
• wherein a cycle of said signal is controlled in accordance with a temperature-dependency of data holding time of said memory cells.

(Amended) A semiconductor memory device with a word pulse generating circuit which has:

• a rectifying device with a temperature-dependent current characteristic;
• a power circuit for generating a power current in response to a current flowing through said rectifying device;
• and
• a delay circuit receiving a power supply from said power circuit and delaying a trigger signal for a word pulse,
• wherein said rectifying device includes a diode connected in series to a power supply, a resistance connected in series between said diode and a ground, and a MOS transistor connected in parallel to said resistance, and a conductive state or a non-conductive state of said MOS transistor is controlled by a state control signal which switches the device between in a stand-by state and in an active state.