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AssigneeEmosyn America, Inc.
InventorsDavid Sowards, Trevor Blyth, Shane C. Hollmer
Estimating the term…
An emulated EEPROM memory array is disclosed based on non-volatile floating gate memory cells, such as Flash cells, where a small group of bits share a common source line and common row lines, so that the small group of bits may be treated as a group during program and erase modes to control the issues of program disturb and effective endurance. The bits common to the shared source line make up the emulated EEPROM page which is the smallest unit that can be erased and reprogrammed, without disturbing other bits. The memory array is physically divided up into groups of columns. One embodiment employs four memory arrays, each consisting of 32 columns and 512 page rows (all four arrays providing a total of 1024 pages with each page having 8 bytes or 64 bits). A global row decoder decodes the major rows and a page row driver and a page source driver enable the individual rows and sources that make up a given array. The page row drivers and page source drivers are decoded by a page row/source supply decoder, based on the addresses to be accessed and the access mode (erase, program or read).
An array of non-volatile floating gate memory cells arranged in a plurality of rows and columns, a plurality of said memory cells electrically coupled to form a plurality of pages, said array comprising:
A method for erasing a memory array comprised of a plurality of non-volatile floating gate memory cells arranged in a plurality of one or more rows and columns, each of said memory cells having a drain, gate and source terminal, a plurality of said memory cells electrically coupled to form a plurality of pages, said method comprising:
A method for avoiding gated diode breakdown in a row driver circuit for a nonvolatile memory array, said row driver circuit having at least two N-channel output driver transistors in series, said row driver circuit capable of switching between a high voltage level and a lower rail voltage in a high voltage mode, said method comprising the steps of:
A row driver circuit for a non-volatile memory array capable of switching between a high voltage level and a lower rail voltage in a high voltage mode, comprising:
A method for avoiding gated diode breakdown in a source driver circuit for a nonvolatile memory array, said source driver circuit having at least two N-channel output driver transistors in series, said source driver circuit capable of switching between a high voltage level and ground, said method comprising the steps of:
Dependencies are inferred from the claim text.