Semiconductor memory device
AssigneeNanya Technology Corporation
InventorsYu-Wen Huang, Shu-Liang Nin
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device. One desired word line of a memory unit is turned on according to the row select signal, and a first delay circuit delays the column select signal a first determined time and outputs to a sense amplifier circuit. The sense amplifier circuit senses the desired word line, amplifies and outputs desired data to a latch circuit according to the column select signal. After that, the memory device can start to access the next data. Further, the delayed column select signal is also output to a second delay circuit to delay a second predetermined time as an output enable signal, and the latch circuit outputs the latched data according to the output enable signal.
Claims8
A semiconductor memory device, comprising:
- a memory array having a plurality of dynamic memory cells, a plurality of word lines and a plurality of bit line pairs, wherein the word lines and the bit line pairs are crisscrossed, and each memory cell is disposed between one of the word lines and one of the bit line pairs;
- a first decoder coupled to the word lines of the memory array, decoding a first address signal and outputting a first select signal to turn on a desired word line of the memory array;
- a sense amplifier circuit coupled to the bit line pairs of the memory array;
- a second decoder for decoding a second address signal, and outputting a second select signal;
- and
- a first delay circuit coupled to the second decoder, delaying the second select signal a first determined time and outputting a sensing enable signal to the sense amplifier circuit;
- wherein the sense amplifier circuit senses a desired bit line pair connected to the desired word line, amplifies and outputs desired data according to the sensing enable signal.
A semiconductor memory device, comprising:
- a memory array having a plurality of dynamic memory cells, a plurality of word lines and a plurality of bit line pairs, wherein the word lines and the bit line pairs are crisscrossed, and each memory cell is disposed between one of the word lines and one of the bit line pairs;
- a row address decoder coupled to the word lines of the memory array, decoding a row address signal and outputting a row select signal to turn on a desired word line of the memory array;
- a sense amplifier circuit coupled to the bit line pairs of the memory array;
- a column address decoder for decoding a column address signal, and outputting a column select signal;
- a first delay circuit coupled to the column address decoder, delaying the column select signal a first determined time and outputting a sensing enable signal to the sense amplifier circuit;
- wherein the sense amplifier circuit senses a desired bit line pair connected to the desired word line, and amplifies and outputs a desired data according to the sensing enable signal;
- a second delay circuit coupled between the first delay circuit and the sense amplifier circuit, delaying the column select signal a second determined time as an output enable signal after receiving the column select signal;
- a latch circuit coupled to the sense amplifier circuit, latching the desired data output from the sense amplifier circuit, and outputting the desired data when receiving the output enable signal;
- an output buffer coupled to the latch circuit for buffering the desired data output from the latch circuit;
- and
- a precharge circuit coupled to the memory array for precharging the bit line pairs of the memory array.
Dependencies are inferred from the claim text.