Two-phase pre-charge circuit and standby current erasion circuit thereof
AssigneeWinbond Electronics Corp.
InventorChieng Chung Chen
Life of this patent
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Abstract
The present invention discloses a two-phase pre-charge circuit and a standby current erasion circuit thereof which is only activated during the active mode for electrically connecting the source of pre-charge voltage and the complementary bit lines. In the standby mode, the two-phase pre-charge circuit is in a disablement state, thereby the short DC standby current between the complementary bit lines and word lines is erased.
Claims6
A two-phase pre-charge circuit for erasing a short DC standby current between a word line and a pair of complementary bit lines of DRAM, comprising:
- a pre-charge equalization circuit, one end of said pre-charge equalization circuit connected to a source of pre-charge voltage and another end connected to said complementary bit lines;
- and
- at least one control signal for generating one pulse in the beginning and end of an active mode of said DRAM for electrically connecting said source of pre-charge voltage and said complementary bit lines, said at least one control signal being disabled in a standby mode of said DRAM.
A short DC standby current erasion circuit of DRAM, comprises a source of pre-charge voltage, a plurality of word lines, a plurality of complementary bit lines and a plurality of pre-charge equalization circuits, characterized in that control signals of the plurality of pre-charge equalization circuits generate a pulse only in the beginning and end of an active mode of said DRAM for electrically connecting said source of pre-charge voltage and said complementary bit lines, said control signals are disabled in a standby mode of said DRAM, thereby the short DC standby current between the complementary bit lines and word lines is erased.
Dependencies are inferred from the claim text.