Sram array with dynamic voltage for reducing active leakage power
AssigneeIntel Corporation
InventorsMuhammad Khellah, Vivek De, Dinesh Somasekhar, Yibin Ye
Life of this patent
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Abstract
A power management device and static random access memory (SRAM) architecture with dynamic supply voltages reduce active power leakage in SRAM cells. When a cell is inactive, a low level supply voltage is applied to the source line connected to the cell to maintain the data stored in the cell. However, before a cell is accessed (e.g., during a read or write operation), the source line is raised to a high level supply voltage.
Claims28
A device comprising:
- a first input configured to receive an indication that a row of a memory array is active or inactive;
- a second input configured to receive a first voltage;
- an output configured to apply the first voltage or a second voltage to a source line of the memory array;
- and
- a power management circuit connected to receive the first and second inputs and configured to apply the second voltage to the output if the row is inactive to reduce active power leakage in the row connected to the source line,
- wherein the second voltage is lower than the first voltage.
A static random access memory (SRAM) comprising:
- one or more cells;
- a source line connected to the cells configured to supply power to the cells;
- and
- a power management device connected to the source line and configured to apply a first voltage to the source line if one of the cells is to be accessed and to apply a second voltage to the source line if none of the cells is to be accessed,
- wherein the second voltage is less than the first voltage and use of the second voltage reduces active power leakage in the cells.
A random access memory (RAM) comprising:
- a row of cells;
- a power grid configured to supply a first voltage;
- a source line connected to the row of cells and configured to supply power to the row of cells;
- a power switch connected to the source line and configured to apply a first voltage to the source line if the row is active;
- and
- one or more power control devices connected between the power grid and the source line and configured to supply a second voltage that is lower than the first voltage to the source line if the row is inactive.
A method for managing active power leakage in a memory array, the method comprising:
- determining if a row in the memory array is active;
- and
- applying a first voltage to a source line connected to the row if the row is determined to be active;
- applying a second voltage to the source line if the row is determined to be inactive,
- wherein the first voltage is greater than the second voltage.
A system comprising:
- a processor;
- a memory array configured to be accessed by the processor;
- and
- a device to manage active power leakage in the memory array, the device including
- a first input configured to receive an indication that a row of the memory array is active or inactive;
- a second input configured to receive a first voltage;
- an output configured to apply the first voltage or a second voltage to a source line of the memory array;
- and
- a power management circuit connected to receive the first and second inputs and configured to apply the second voltage to the output if the row is inactive to reduce active power leakage in the row connected to the source line,
- wherein the second voltage is lower than the first voltage.
Dependencies are inferred from the claim text.