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US 2003/0189847 A1Published application
SEU resistant SRAM using feedback MOSFET
AssigneeHoneywell International Inc.
InventorsMichael S. Liu, Shankar P. Sinha
Life of this patent
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Abstract
A random access memory cell has first and second inverters each having an input and an output. The input of the first inverter is coupled to the output of the second inverter by a Schottky-diode-free MOSFET. The input of the second inverter is coupled to the output of the first inverter.
Claims24
A random access memory cell comprising:
- a first inverter having an input and an output;
- a second inverter having an input and an output;
- wherein the input of the first inverter is coupled to the output of the second inverter by only one device having a junction, and wherein the device comprises a MOSFET;
- and,
- wherein the input of the second inverter is coupled to the output of the first inverter.
2 more elements
A random access memory cell comprising:
- a first inverter having an input and an output;
- a second inverter having an input and an output;
- a first transmission gate coupled to the input of the first inverter;
- a second transmission gate coupled to the input of the second inverter;
- wherein the input of the first inverter is coupled to the output of the second inverter by only one active device, and wherein the device comprises a MOSFET;
- and,
- wherein the input of the second inverter is coupled to the output of the first inverter.
4 more elements
A random access memory cell comprising:
- first, second, third, fourth, fifth, and sixth MOSFETs each having a gate, a source, and a drain;
- a Schottky-diode-free seventh MOSFET having a gate, a source, and a drain;
- wherein the gates of the third and fourth MOSFETs are coupled together;
- wherein the gates of the fifth and sixth MOSFETs are coupled together;
- wherein the sources of the third and fifth MOSFETs are coupled together;
- wherein the drains of the fourth and sixth MOSFETs are coupled together;
- wherein the drain of the third MOSFET is coupled to the source of the fourth MOSFET;
- wherein the drain of the fifth MOSFET is coupled to the source of the sixth MOSFET;
- wherein the gates of the third and fourth MOSFETS are coupled to the drain of the fifth MOSFET and to the source of the sixth MOSFET through the source and drain of the Schottky-diode-free seventh MOSFET;
- wherein the gates of the fifth and sixth MOSFETs are coupled to the drain of the third MOSFET and to the source of the fourth MOSFET;
- wherein one of the source and drain of the first MOSFET is coupled to the gates of the third and fourth MOSFETs;
- wherein one of the source and drain of the second MOSFET is coupled to the gates of the fifth and sixth MOSFETs;
- and,
- wherein the gates of the first and second MOSFETs are coupled to a write line.
11 more elements
Dependencies are inferred from the claim text.