US 2003/0189845 A1 · Semiconductor device having redundancy circuit

Abstract

A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

Claims11

Dependent claims

A semiconductor memory comprising:

a memory mat comprised of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells;
and
an address comparing circuit, which stores high and low logical values and a don't care value, comprising a plurality of bit comparing circuits and a plurality of first N-channel MOS transistors each having a source/drain current path and a gate,
wherein said first N-channel MOS transistors are coupled in series via the source/drain current paths thereof, a first end of the series-coupled N-channel MOS transistors being precharged by a precharge signal, and
wherein each of said bit comparing circuits has an output coupled to control the gate of a respective one of said first N-channel MOS transistors.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/401,975Filed 31 Mar 2003

Priority

JP 63-2520287 Oct 1988

Published

9 Oct 2003

Term ends

Not estimatedThe source records don’t support an estimate.