Circuit and method for data output in synchronous semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsJin-Seok Kwak, Seong-Jin Jang
Life of this patent
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Abstract
A data output circuit and method in a synchronous semiconductor device are described. The semiconductor device is preferably a wave pipelined synchronous semiconductor device. A first-stage or former-stage latch unit receives a first bit of a group of data bits to be output. A second-stage or latter-stage latch unit receives a second bit of the group of data bits. A buffering unit is interposed between the first and second stage latch units. The buffering unit receives the second bit from the second-stage latch unit and forwards the second bit to the first-stage latch unit.
Claims37
A data output circuit in a synchronous semiconductor device for providing a set of data bits as an output, comprising:
- a first-stage latch unit for receiving a first bit of the data bits in response to a first control signal;
- a second-stage latch unit for receiving a second bit of the data bits in response to the first control signal;
- and
- a buffering latch unit interposed between the first-stage latch unit and the second-stage latch unit, the buffering latch unit receiving the second bit from the second-stage latch unit and forwarding the second bit to the first-stage latch unit in response to a second control signal.
A data output method in a synchronous semiconductor device for providing a set of data bits as an output, comprising:
- providing a first-stage latch unit for receiving a first bit of the data bits in response to a first control signal;
- providing a second-stage latch unit for receiving a second bit of the data bits in response to the first control signal;
- and
- providing a first buffering latch unit interposed between the first-stage latch unit and the second-stage latch unit, the first buffering latch unit receiving the second bit from the second-stage latch unit and forwarding the second bit to the first-stage latch unit in response to a second control signal.
A data output circuit in a synchronous semiconductor device for providing a set of data bits as an output, comprising:
- a first data output unit for receiving a first subset of bits of the set of data bits, the first data output unit comprising:
- a first first-stage latch unit for receiving a first bit of the first subset of bits in response to a first control signal;
- a first second-stage latch unit for receiving a second bit of the first subset of bits in response to the first control signal;
- and
- a first buffering latch unit interposed between the first first-stage latch unit and the first second-stage latch unit, the first buffering latch unit receiving the second bit of the first subset of bits from the first second-stage latch unit and forwarding the second bit of the first subset of bits to the first first-stage latch unit in response to a second control signal;
- and
- a second data output unit for receiving a second subset of bits of the set of data bits, the second data output unit comprising:
- a second first-stage latch unit for receiving a first bit of the second subset of bits in response to a third control signal;
- a second second-stage latch unit for receiving a second bit of the second subset of bits in response to the third control signal;
- and
- a second buffering latch unit interposed between the second first-stage latch unit and the second second-stage latch unit, the second buffering latch unit receiving the second bit of the second subset of bits from the second second-stage latch unit and forwarding the second bit of the second subset of bits to the second first-stage latch unit in response to a fourth control signal.
Dependencies are inferred from the claim text.