Array substrate for liquid crystal display device and manufacturing method thereof
AssigneeLG.Philips LCD Co., Ltd.
InventorByeong Dae Choi
Life of this patent
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Abstract
An array substrate for a liquid crystal display device includes a substrate, a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel area, a thin film transistor electrically connected to the gate and data line and includes a gate electrode, an active layer, a source electrode, and a drain electrode, a passivation layer covering the gate line, the data line, and the thin film transistor, and having a contact hole situated on the active layer to expose portions of the drain electrode and the active layer, and a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole.
Claims17
An array substrate for a liquid crystal display device, comprising:
- a substrate;
- a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel area;
- a thin film transistor electrically connected to the gate and data line and includes a gate electrode, an active layer, a source electrode, and a drain electrode;
- a passivation layer covering the gate line, the data line, and the thin film transistor, and having a contact hole situated on the active layer to expose portions of the drain electrode and the active layer;
- and
- a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole.
A manufacturing method of an array substrate for a liquid crystal display device, comprising:
- forming a gate line and a gate electrode on a substrate through a first mask process;
- forming a gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, and a metal layer on the gate line and the gate electrode;
- forming a photoresist layer on the metal layer;
- forming a photoresist pattern by exposing and developing the photoresist layer through a second mask process, the photoresist layer having a first thickness and a second thickness thinner than the first thickness;
- patterning the metal layer, the doped amorphous silicon layer, and the amorphous silicon layer exposed by the photoresist pattern to form a source and drain pattern, a data line, a doped amorphous silicon pattern, and an active layer;
- removing the second thickness of the photoresist pattern through an ashing process to expose the source and drain pattern;
- patterning the source and drain pattern and the doped amorphous silicon pattern exposed by the photoresist pattern to form a source electrode, a drain electrode, and an ohmic contact layer;
- forming a passivation layer on the source and drain electrodes;
- patterning the passivation layer through a third mask process to form a contact hole situated on the active layer and exposing the drain electrode and the active layer;
- and
- forming a pixel electrode on the passivation layer through a fourth mask process, the pixel electrode connected to the drain electrode through the contact hole.
Dependencies are inferred from the claim text.