Parallel processing processor and parallel processing method

A parallel processing processor for processing images including α data indicative of pixel transparency, said parallel processing processor comprising:

• (a) a plurality of execution units for executing in parallel arithmetic and logical operations under control of a single instruction;
• (b) general purpose registers which are connected to said execution units via a data path, which input data to said execution units and which receive results of operations from said execution units;
• and
• (c) α data dedicated registers which are connected to said execution units via another data path and which input data to said execution units;
• wherein, under control of a single instruction, said execution units admit data from said general purpose registers to carry out first arithmetic and logical operation on the admitted data and, without returning result of said first arithmetic and logical operation to said general purpose registers, receive data from said α data dedicated registers to perform second arithmetic and logical operation between the received data and the result of said first arithmetic and logical operation.

A parallel processing method for use with a plurality of execution units for executing in parallel arithmetic and logical operations under control of a single instruction, said parallel processing method processing images including α data indicative of pixel transparency and comprising the steps of:

• (a) inputting a plurality of first data from general purpose registers to said execution units for performing first arithmetic and logical operation in parallel by the units;
• (b) inputting a plurality of second data corresponding to said first data from α data dedicated registers to said execution units without returning result of said first arithmetic and logical operation to said general purpose registers, so as to perform second arithmetic and logical operation in parallel between said second data and said result of said first arithmetic and logical operation;
• and
• (c) outputting result of said second arithmetic and logical operation to a general purpose register designated by an instruction.