US 2003/0189544 A1 · Display control circuit for liquid crystal display

Abstract

When count values CNT of a counter 11 are values other than 1, a selection signal SEL of a decode section 18 becomes “H”, so that a clock signal CLK is selected by a selection section 17 and it is inputted into the counter 11 and a shift section 15 as a display clock signal DCK. When the count value CNT becomes 1, the selection signal SEL becomes “L”, so that a clock signal CLK divided into ½ by a division section 16 is selected in the selection section 17 and outputted as the display clock signal DCK. Thereby, the count value CNT is maintained to be 1 for two cycles of the clock signal CLK. Thereby, the pulse width of a common signal C1 outputted from the shift section 15 becomes two times the pulse width of the other common signals C2 to C33. Therefore, large pixels driven on the basis of the common signal C1 can be displayed with the same contrast.

Claims20

Dependent claims

A display control circuit for a liquid crystal display which comprises a plurality of common electrodes and a plurality of segment electrodes arranged so as to cross the common electrodes, for performing displaying according to common signals applied to the common electrodes and signals applied to the segment electrodes, comprising:

dividing circuit which divides a clock signal of a constant cycle to generate divided clock signals;
selecting circuit which selects one of the clock signal and the divided clock signal according to a selection signal to output the selected one as a display clock signal;
counting circuit which counts the number of pulses of the display clock signal to output count values in a predetermined range sequentially and repeatedly;
decoding circuit which outputs a selection signal for causing the selecting circuit to select the divided clock signal when the count value has reached a preset value;
and
common signal generating circuit which generates common signals to sequentially drive common electrodes according to the display clock signal.

3 more elements

dividing circuit which divides a clock signal of a constant cycle to first and second generate divided clock signals;
selecting circuit which selects one of the first and second divided clock signals according to a selection signal to output the selected one as a display clock signal;
counting circuit which counts the number of pulses of the display clock signal to output count values in a predetermined range sequentially and repeatedly;
decoding circuit which outputs a selection signal for causing the selecting circuit to select the second divided clock signal when the count value has reached a preset value;
and
common signal generating circuit which generates common signals to sequentially drive common electrodes according to the display clock signal.

3 more elements

Dependencies are inferred from the claim text.

Display control circuit for liquid crystal display

Life of this patent

Display control circuit for liquid crystal display

Life of this patent

Abstract

Claims20