US 2003/0189471 A1 · BIAS FEED NETWORK ARRANGEMENT FOR BALANCED LINES

Abstract

A circuit configuration for introducing bias in balanced lines capable of high frequency operation comprises top and bottom layers formed on a semiconductor substrate. The circuit includes two balanced metallized lines positioned on the substrate. Each metallized line has a serpentine line configuration connected thereto. The space between the lines is a virtual ground. The serpentine line configurations are congruent with the elements on the substrate layers to provide a completed circuit. The elements are coupled to a central metallic area, which in turn is coupled to a bias line through an open-line stub, which extends beyond the virtual ground and which provides equal capacitive coupling to the balanced lines on the top surface. In this manner, the balanced line configuration includes capacitors and inductors which are symmetrically distributed and which provide resonance at the designed operating frequency. The bias line thus formed is RF grounded due to the virtual ground and is disconnected from the actual balanced lines.

Claims20

Dependent claims

A balanced line network for use with lossy semiconductor substrates, comprising:

first and second spaced apart parallel balanced conductive lines directed from a first end to a second end of said substrate and positioned on a top surface of said substrate, each line coupled to a symmetrically positioned transverse high impedance line which, as positioned, are shielded by said first and second lines, and are positioned to form first symmetrical inductive reactances for said line,
an insulating layer formed on said substrate and having a metallized area located thereon and symmetrically positioned between said first and second lines and said high impedance lines to provide a balanced capacitive reactance for said lines, said metallized area connected to symmetrically high impedance lines which are positioned to co-act with said high impedance lines on a top surface of said layer to form second symmetrical inductive reactance for said lines, wherein said inductive reactances and said capacitive reactances resonate at a desired frequency and where the reactances are all referenced to the virtual ground as the space between said parallel balanced lines, and
a bias line connected to said virtual ground.

A balanced line network configuration adapted for bias circuit feed, comprising:

a substrate having a top surface and a bottom surface,
first and second metallized conductive lines positioned on said top surface relatively parallel to each other and separated by a predetermined distance,
a first serpentine structure connected to said first line at a given point forming a first high impedance element,
a second serpentine structure connected at said given point to said second line forming a second high impedance structure,
a metallized area positioned on said substrate and symmetrically positioned about said common point between said first and second lines,
a third serpentine structure connected to said metallized area at said common point with respect to said first serpentine structure to provide a first symmetrical inductive reactive element for said first and second lines, and connected to the first serpentine structure,
a fourth serpentine structure connected to said metallized area at said common point opposite said first side and positioned with respect to said second top serpentine structure to provide a second symmetrical inductive reactive element for said first and second lines, with said first and second inductive reactive elements coupled together, said metallized area of said substrate providing a symmetrical capacitive reactance between said first and second lines,
a virtual ground located at the center of the space between said first and second lines whereby a bias conductive line can be connected to said virtual ground to form a RF bias line for said balanced line network.

5 more elements

Dependencies are inferred from the claim text.

Bias feed network arrangement for balanced lines

Life of this patent

Bias feed network arrangement for balanced lines

Life of this patent

Abstract

Claims20