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US 2003/0189455 A1Published application
CMOS transmission gate with high impedance at power off
AssigneeExar Corporation
InventorBahram Fotouhi
Life of this patent
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Abstract
A transmission gate circuit with high impedance during power off conditions, which includes a first transistor coupled between a first terminal and a second terminal and a second transistor coupled between the first terminal and the second terminal. Also included is a control circuit configured to monitor voltages on the first terminal and on a first voltage source, the control circuit configured to couple the gates of the first and second transistors to a voltage that will keep the first and second transistors off during power off conditions.
Claims8
A transmission gate circuit comprising:
- a first transistor coupled between a first terminal and a second terminal;
- a second transistor coupled between the first terminal and the second terminal;
- and
- a control circuit configured to monitor voltages on the first terminal and on a first voltage source, wherein the control circuit is configured to couple the gates of the first and second transistors to a voltage that will keep the first and second transistors off during power off conditions.
1 more element
Dependencies are inferred from the claim text.