Low-power CMOS flip-flop
AssigneeThe Regents of the University of Michigan
InventorsConrad H. Ziesler, Marios C. Papaefthymiou
Life of this patent
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Abstract
A flip-flop includes a charge storage area that stores a logic voltage indicating a logic state of the flip-flop, a first transistor having a source or drain connected to a clock signal generating circuit, a second transistor having a source or drain connected to the clock signal generating circuit, a clock signal generated by the clock signal generating circuit that is ramped or sinusoidal, and a latching circuit that latches a latch voltage value based on voltages at the first transistor and the second transistor. The charge storage area supplies a first voltage representing a state of the storage voltage to a gate of the first transistor and supplies a second voltage to a gate of the second transistor.
Claims24
A flip-flop, comprising:
- an input value that provides a logic voltage indicating a logic state of the flip-flop;
- at least a first transistor connected to a clock signal generating circuit at a source or drain of the first transistor;
- at least a second transistor connected to a clock signal generating circuit at a source or drain of the second transistor;
- a clock signal generated by the clock signal generating circuit that is ramped or sinusoidal;
- and
- a latching circuit that latches a latch voltage value based on a first clock voltage at a first connection point and a second connection point, wherein the latch voltage is representative of the input value;
- wherein the first connection point is a source or drain of the first transistor that is opposite to the clock signal generating circuit;
- and
- wherein the second connection point is a source or drain of the second transistor that is opposite the clock signal generating circuit.
A method for operating a low-power flip-flop with a single input clock signal of ramped or sinusoidal shape, comprising:
- setting a first transistor and a second transistor of a flip-flop in an ON/OFF condition representative of an input value to the flip-flop that represents a logic state of the flip-flop;
- driving sources or drains of the first transistor and the second transistor with a ramped clock signal;
- and
- latching voltages at sources or drains opposite to that which is being driven by the clock signal to latch the logic state of the flip-flop.
Dependencies are inferred from the claim text.