Semiconductor device and method for manufacturing the same

A semiconductor device in which a plurality of semiconductor chips is stacked in layers and sealed in a package, comprising:

• a lower-layer semiconductor chip which is mounted on a package board;
• an upper-layer semiconductor chip which is stacked via a plurality of spacers on said lower-layer semiconductor chip;
• at least one first conductor interconnecting electrically at least one first electrode on said lower-layer semiconductor chip and at least one first internal terminal on said package board;
• at least one second conductor electrically interconnecting at least one second electrode on said upper-layer semiconductor chip and at least one second internal terminal on said package board;
• and
• said package sealing therein said lower-layer semiconductor chip, said upper-layer semiconductor chip, and said at least one first conductor and said at least one second conductor which are all on said package board.

A semiconductor device manufacturing method for stacking a plurality of semiconductor chips in layers and sealing said plurality of semiconductor chips in a package, comprising the steps of:

• forming a plurality of spacers on a lower-layer semiconductor chip;
• stacking an upper-layer semiconductor chip via said plurality of spacers on said lower-layer semiconductor chip;
• and
• sealing said lower-layer semiconductor chips, said plurality of spacers, and said upper-layer semiconductor chip in an insulating material making up said package.

A semiconductor device manufacturing method for stacking a plurality of semiconductor chips in layers and sealing said plurality of semiconductor chips in a package, comprising:

• a lower-layer semiconductor chip mounting step of mounting a lower-layer semiconductor chip on a package board;
• a first connecting step of interconnecting electrically at least one first internal terminal on said package board and at least one first electrode on said lower-layer semiconductor chip using at least one first conductor;
• a spacer formation step of forming a plurality of spacers on said lower-layer semiconductor chip;
• an upper-layer semiconductor chip stacking step of stacking an upper-layer semiconductor chip via said plurality of spacers on said lower-layer semiconductor chip;
• a second connecting step of interconnecting electrically at least one second internal terminal on said package board and at least one second electrode on said upper-layer semiconductor chip using at least one second conductor;
• and
• a sealing step of sealing said lower-layer semiconductor chip, said upper-layer semiconductor chip, and said at least one first conductor and said at least one second conductor in an insulating material making up said package.