Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit

A dual damascene structure for electrically interconnection to a base metal interconnect structure formed in a semiconductor substrate, which comprises:

• a first dielectric layer formed from a first low-K inorganic dielectric material over the substrate to cover the exposed surface of the base metal interconnect structure:
• an etch-stop layer formed from a low-K organic dielectric material over the first dielectric layer;
• a second dielectric layer formed from a second low-K inorganic dielectric material over the etch-stop layer;
• and
• a pair of metal plugs including a first metal plug and a second metal plug, the first metal plug penetrating successively through the second dielectric layer, the etch-stop layer, and the first dielectric layer to come into electrical contact with the base metal interconnect structure in the substrate, and the second metal plug penetrating through the second dielectric layer to come into contact with the etch-stop layer.