Microelectronic package with reduced underfill and methods for forming such packages
AssigneeMicron Technology, Inc.
InventorsTongbi Jiang, Farrah J. Storli
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsTongbi Jiang, Farrah J. Storli
Estimating the term…
A microelectronic package and method for manufacture. The package can include a support member and a microelectronic substrate positioned at least proximate to the support member. The microelectronic substrate can have a first surface and a second surface facing opposite the first surface, with the first surface having an outer edge and facing toward the support member. At least a portion of the first surface can be spaced apart from an interior surface of the support member to define an intermediate region. At least one conductive coupler is coupled between the microelectronic substrate and the support member. A generally electrically non-conductive material is positioned in the intermediate region with the material contacting the support member and the first surface of the microelectronic substrate and having an outer surface recessed inwardly from the outer edge of the microelectronic substrate.
A microelectronic package, comprising:
A microelectronic package, comprising:
A packaged microelectronic device, comprising:
A microelectronic package, comprising:
A microelectronic device package, comprising:
A method for forming a microelectronic package, comprising:
A method for forming a microelectronic package, comprising:
A method for forming a microelectronic package, comprising:
Dependencies are inferred from the claim text.