Loading patent…
AssigneeNational Chiao Tung University
InventorsBing-Yue Tsui, Chih-Feng Huang
Estimating the term…
The present invention provides a structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which comprises a SOI (Silicon-On-Insulator) device, a MOS (Metal Oxide Semiconductor) formed on said SOI device, and a metal-silicide layer. Said SOI device includes a substrate, an insulation layer formed on said substrate, and a silicon layer formed on said insulation layer, and the MOS is formed on said SOI device. The metal-silicide layer is formed in accordance with a metal aligned process by a metal layer being deposited on said SOI device and on said MOS for reacting with said silicon layer, and an implant-to-silicide process is employed to form a high-density source region and a high-density drain region for modifying Schottky Barrier and diminishing Carrier Injection Resistance.
1 A structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for modifying Schottky Barrier and diminishing Carrier Injection Resistance, which comprises:
2 The structure of claim 1, wherein said MOS is selected from one of P-MOS or N-MOS.
3 The structure of claim 1, wherein said MOS further comprises a channel between said source electrode and said drain electrode for carriers passing through.
4 The structure of claim 1, wherein said substrate is selected from one of a silicon substrate or a glass substrate.
5 The structure of claim 1, wherein said insulation layer is an oxide layer.
6 A structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for modifying Schottky Barrier and diminishing Carrier Injection Resistance, which comprises:
7 The structure of claim 6, wherein said MOS is selected from one of P-MOS or N-MOS.
8 The structure of claim 6, wherein said MOS further comprises a channel between said source electrode and said drain electrode for carriers passing through.
9 The structure of claim 6, wherein said substrate is selected from one of a silicon substrate or a glass substrate.
10 The structure of claim 6, wherein said insulation layer is an oxide layer.
11 A method for fabricating MOSFET for modifying Schottky Barrier and diminishing Carrier Injection Resistance, which comprises the steps of:
12 The method of claim 11, wherein the step of reacting with said silicon layer to form a metal-silicide layer by a metal self-aligned process may be changed with the step of implant-to-metal process, which forms a high-density source region and a high-density drain region first, and then reacts with said silicon layer to form said metal-silicide layer for modifying the Schottky Barrier for diminishing Carrier Injection Resistance.
13 The method of claim 11, after forming said metal-silicide layer further comprises the step of annealing process, wherein the implant-to-silicide for implanting carriers into said silicide layer processing, then processing the step of annealing.
14 The method of claim 11, wherein said MOS is selected from one of P-MOS or N-MOS.
15 The method of claim 11, wherein said MOS further comprises a channel between said source electrode and said drain electrode for carriers passing through.
16 The method of claim 11, wherein said substrate is selected from one of a silicon substrate or a glass substrate.
17 The method of claim 11, wherein said insulation layer is an oxide layer.