Printed wiring board

A process for making a printed wiring board (PWB) structure comprising the steps of:

• providing an electrically conductive power plane having a first plane side and a second plane side and one or more via holes formed and extending through said electrically conductive power plane from said first plane side to said second plane side;
• applying a photo-imageable dielectric (PID) material to said first and second plane sides of said electrically conductive power plane substantially filling said one or more via holes forming filled via holes;
• placing a photo-mask on said first plane side of said electrically conductive power plane;
• exposing said photo-mask on said first plane side of said electrically conductive power plane to light energy to substantially cure all of said PID material in said filled via holes;
• and
• applying a developer to said electrically conductive power plane after said exposing step, said developer removing substantially all of said PID material that remains uncured after said exposing step.

A printed wiring board (PWB) comprising:

• an electrically conductive power plane having first and second plane surfaces and one or more filled via holes extending from said first plane surface to said second plane surface, said one or more filled via holes substantially filled with a photo-imageable dielectric (PID) material that has been cured with light energy;
• a first signal plane assembly having a first electrically conductive signal plane bonded to a first dielectric layer of a uniform first thickness, said first dielectric layer laminated to said first plane surface of said electrically conductive power plane;
• and
• a second signal plane assembly having a second electrically conductive signal plane bonded to a second dielectric layer of a uniform second thickness, said second dielectric layer laminated to said second plane surface of said electrically conductive power plane, wherein portions of said first dielectric layer further fill any unfilled surface areas of said filled via holes on said first plane surface and portions of said second dielectric layer further fill any unfilled surface areas of said filled via holes on said second plane surface.