Utilization of unused IO block for core logic functions
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsRajat Chauhan, Rajesh Kaushik
Life of this patent
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Abstract
A method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions is provided, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.
Claims50
In an FPGA apparatus, an improvement for enabling the selective utilization of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions, comprising:
- disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and
- connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.
A method for enabling the utilization of unused flip-flops or other unused circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUTs) of an FPGA for core logic functions, comprising the steps of:
- disconnecting said unused circuit elements from said IO circuitry and/or LUT, and
- connecting said disconnected circuit elements to the connection matrix of the core logic or amongst themselves to provide independent functions.
A field-programmable gate array, comprising:
- an input-output pad;
- a logic core;
- and
- an input-output logic block coupled to the input-output pad and to the logic core and operable to couple data between the input-output pad and the core and to perform a logical operation on data.
A field-programmable gate array, comprising:
- input-output pads;
- a logic core;
- input-output logic blocks each coupled to a respective one of the input-output pads and to the logic core and each operable to couple data between the respective input-output pad and the core and to perform a respective logical operation on data.
A field-programmable gate array, comprising:
- an input-output pad;
- a logic core;
- and
- an input-output logic block coupled to the input-output pad and to the logic core and operable to couple data between the input-output pad and the core and to multiplex data.
A method, comprising:
- receiving data with an input-output logic block of a field-programmable gate array;
- and
- performing on the data with the input-output logic block a logical operation other than coupling the data between an input-output pad and a logic core.
A method, comprising:
- receiving data with input-output logic blocks of a field-programmable gate array;
- and
- performing on the data with the input-output logic blocks a logical operation other than coupling the data between an input-output pad and a logic core.
A method, comprising:
- receiving data values with an input-output logic block of a field-programmable gate array;
- and
- selecting one of the data values with the input-output logic block.
Dependencies are inferred from the claim text.