Method for performing multi-clock static timing analysis
AssigneeVIA Technologies, Inc.
InventorYou-Ming Chiu
Life of this patent
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Abstract
A method for performing multi-clock static timing analysis to determine whether a timing violation occurs on a logic circuit. A set of clock signals that are expected to cause a logic circuit to be in a worst-case situation if analyzed by using static timing analysis can be selected from a number of possible clock signals by using a simple determination process. The selected set of clock signals are then employed in static timing analysis on the logic circuit to verify whether no timing violation occurs on each signal transmission path of the logic circuit. If not, it indicates that the logic circuit using any selection of the possible clock signals will not cause timing violation thereon. Thus, the static timing analysis can be accomplished efficiently
Claims24
A method for performing multi-clock static timing analysis to determine whether a timing violation occurs on a sequential logic circuit including a first sequential logic gate, a combinational logic circuit, and a second sequential logic gate, wherein an output signal outputted from the first sequential logic gate is transmitted to the second sequential logic gate via a plurality of signal transmission paths of the combinational logic circuit;
- a clock input terminal of the first sequential logic gate is used to receive one of a plurality of source clock signals;
- and a clock input terminal of the second sequential logic gate is used to receive one of a plurality of destination clock signals, the method comprising the steps of:
- determining a plurality of source-to-destination edge time margins by comparison of each of the destination clock signals with each of the source clock signals;
- selecting a smallest edge time margin from the source-to-destination edge time margins, wherein the smallest edge time margin is associated with one of the source clock signals and one of the destination clock signals;
- and
- determining whether a timing violation occurs on the signal transmission paths by performing static time analysis on the sequential logic circuit using the source clock signal and the destination clock signal which both are associated with the smallest edge time margin.
A method for performing multi-clock static timing analysis to determine whether a timing violation occurs on a sequential logic circuit including a first sequential logic gate, a combinational logic circuit, and a second sequential logic gate, wherein an output signal outputted from the first sequential logic gate is transmitted to the second sequential logic gate via a plurality of signal transmission paths of the combinational logic circuit, a clock input terminal of the first sequential logic gate is used to receive one of M source clock signals, and a clock input terminal of the second sequential logic gate is used to receive one of N destination clock signals, in which M and N are positive integers, the method comprising the steps of:
- determining M*N source-to-destination edge time margins by comparison of each of the M source clock signals with each of the N destination clock signals;
- selecting a smallest edge time margin from the source-to-destination edge time margins, wherein the smallest edge time margin is associated with one of the source clock signals and one of the destination clock signals;
- and
- determining whether a timing violation occurs on the signal transmission paths by performing static time analysis on the sequential logic circuit using the source clock signal and the destination clock signal which both are associated with the smallest edge time margin.
Dependencies are inferred from the claim text.