Interconnect-aware methodology for integrated circuit design
AssigneeInternational Business Machines Corporation
InventorsAmir Alon, David Goren, Rachel Gordin, Betty Livshitz, Anatoly Sherman, Michael Zelikson
Life of this patent
Estimating the term…
Abstract
An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The kit may further include one or more circuit components models and one or more critical interconnect lines models.
Claims30
A system for integrated circuit design comprising:
- a high level design comprising a chip architecture, a floor plan, and one or more critical interconnect wire topologies;
- a schematic design comprising one or more circuit components and one or more critical interconnect wire models;
- a physical layout comprising said one or more circuit components and said one or more critical interconnect wire topologies;
- extracted parameters of said one or more circuit components and calculated parameters of said critical interconnect wire models;
- and
- results of a simulation of a schematic design comprising said extracted parameters and said calculated parameters.
An integrated circuit design kit comprising:
- one or more circuit components topologies;
- and
- one or more critical interconnect lines topologies.
A topology of critical interconnect lines.
A computer software product for designing an integrated circuit, said product comprising a computer readable medium in which program instruction are stored, which instructions, when read by a computer, cause said computer to create a topology of critical interconnect lines.
A computer software product for designing an integrated circuit, said product comprising a computer readable medium in which program instruction are stored, which instructions, when read by a computer, cause said computer to create a design kit comprising a topology of critical interconnect lines.
A method for designing integrated circuits (IC), said method comprising the steps of:
- (a) defining a chip architecture and a floor plan;
- (b) identifying one or more critical interconnect lines, and defining transmission line topologies for design of said critical interconnect lines;
- (c) determining a schematic design of said IC;
- (d) defining a physical layout of said IC;
- (e) extracting electrical parameters of said layout;
- (f) simulating said schematic design;
- and
- (g) receiving results of said simulation.
A method for designing integrated circuits wherein defining said chip architecture and a floor plan comprises defining critical interconnect wires.
Dependencies are inferred from the claim text.