Technique for debugging an integrated circuit having a parallel scan-chain architecture
AssigneeAgilent Technologies, Inc.
InventorsIsmed D.S. Hartano, Fidel Muradali, John S. Walther
Life of this patent
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Abstract
The present disclosure describes a technique for debugging an integrated circuit having a parallel scan-chain architecture. Blocking circuits are introduced at the inputs and/or outputs of scan-chain branches. The blocking circuits allow the inputs to and/or the outputs from the scan-chain branches to be selectively blocked. This allows individual scan-chain branches to be isolated and debugged.
Claims18
An integrated circuit device comprising:
- a plurality of scan-chain branches, each scan-chain branch including a plurality of storage elements;
- and
- a plurality of output blocking circuits, each output blocking circuit having a first input coupled to a respective output of each scan-chain branch, each output blocking circuit operable to block the output of a respective scan-chain branch.
An integrated circuit device comprising:
- a plurality of scan-chain branches, each scan-chain branch including a plurality of storage elements;
- and
- a plurality of input blocking circuits, each input blocking circuit having an output coupled to a respective input of each scan-chain branch, each input blocking circuit operable to block the input of a respective scan-chain branch.
A method for debugging an integrated circuit device having a plurality of scan-chain branches, the method comprising:
- blocking the outputs of at least one of the scan-chain branches;
- scanning resulting data bits out of the integrated circuit device;
- and
- comparing the resulting data bits with expected data bits to determine the location of one or more faults.
Dependencies are inferred from the claim text.