Built-in self test parallel JTAG serial chain architecture for reduced test vector size
OwnerEric R. Wehageinventor
Life of this patent
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Abstract
A system and method for programming built-in self-testing (BIST) state machines to test integrated circuit components are disclosed. The standard Joint Test Action Group method for programming BIST state machines is modified to increase speed and efficiency. The registers containing the instructions for BIST testing are connected in parallel, as opposed to the standard serial connections, allowing the registers to be fed instructions simultaneously. This cuts down the required time to feed test instructions to the BIST state machines. The addition of multiple shadow registers to each register further cuts down the required time to feed test instructions to the BIST state machines.
Claims25
An integrated circuit, comprising:
- a plurality of built in self testing (BIST) state machines to test a set of integrated circuit components;
- and
- a plurality of shift chains of registers, each of the plurality of shift chains of registers being coupled to one of the plurality of BIST state machines to store a set of data related to the one BIST state machine, with at least two of the shift chain of registers being connected in parallel.
An integrated circuit, comprising:
- a plurality of built in self testing (BIST) state machines to test the set of integrated circuit components;
- a plurality of shift chains of registers, wherein each of the plurality of shift chains of registers is coupled to one of the plurality of BIST state machines to store a set of data related to the one BIST state machine;
- and
- a plurality of sets of shadow registers for each register to transfer data between the BIST state machine and the shift chain of registers.
A method, comprising:
- executing instructions with a plurality of built in self testing (BIST) state machines and a plurality of shift chains of register on an integrated circuit to test at least one component of the integrated circuit, wherein at least one of the plurality of shift chains of registers is connected to each BIST state machine to store a set of data related to the BIST state machine and is connected to another of the plurality of shift chains of registers in parallel;
- and
- shifting data from one or the parallel-connected shift chains of registers into one of two sets of shadow registers associated with the one parallel-connected shift chain of registers.
Dependencies are inferred from the claim text.