Method and apparatus for enhancing input/output error analysis in hardware sub-systems

A data processing system comprising:

• an input/output bus;
• a plurality of processors connected to the input/output bus;
• and
• a hierarchical hardware subsystem including a host bridge and a set of components, wherein the host bridge includes a set of mapping registers and a set of control and status registers in which the set of control and status registers includes an error register, wherein the set of mapping registers are frozen in response to an error and wherein the error register is used to write addresses to registers in the set of components to retrieve data for error analysis.

A data processing system for processing errors in a hierarchical hardware sub-system in the data processing system in which the hierarchical hardware sub-system includes a host bridge having a mapping registers section and a control and status registers section, the data processing system comprising:

• a bus system;
• a communications unit connected to the bus system;
• a memory connected to the bus system, wherein the memory includes a set of instructions;
• and
• a processing unit connected to the bus system, wherein the processing unit executes the set of instructions to identify a component within the hierarchical hardware sub-system connected to the host bridge to form a selected component in response to detecting an error freezing the mapping registers section in the host bridge;
• write an address to a register within the control and status registers section of the host bridge in which the address is to an error register in the component;
• and read data in response to a result being placed in the control and status registers portion of the host bridge.

A data processing system for processing errors in a hierarchical hardware sub-system in the data processing system, wherein the hierarchical hardware sub-system includes a host bridge having a mapping registers section and a control and status registers section, the data processing system comprising:

• identifying means, responsive to detecting an error freezing the mapping registers section in the host bridge, for identifying a component within the hierarchical hardware sub-system connected to the host bridge to form a selected component;
• writing means for writing an address to a register within the control and status registers section of the host bridge, wherein the address is to an error register in the component;
• and
• reading means for reading data in response to a result being placed in the control and status registers portion of the host bridge.

A computer program product in a computer readable medium for processing errors in a hierarchical hardware sub-system in the data processing system, wherein the hierarchical hardware sub-system includes a host bridge having a mapping registers section and a control and status registers section, the computer program product comprising:

• first instructions, responsive to detecting an error freezing the mapping registers section in the host bridge, for identifying a component within the hierarchical hardware sub-system connected to the host bridge to form a selected component;
• second instructions for writing an address to a register within the control and status registers section of the host bridge, wherein the address is to an error register in the component;
• and
• third instructions for reading data in response to a result being placed in the control and status registers portion of the host bridge.