Method and apparatus for analyzing hardware errors in a logical partitioned data processing system

A method in a data processing system for processing errors in an input/output sub-system, the method comprising:

• responsive to detecting an error, reading a value from a selected register to form a read value;
• resetting the selected register;
• clearing each bit in the read value associated with the error to form a cleared value;
• and
• writing the cleared value into the selected register such that errors occurring since the register was cleared are preserved.

A method in a data processing system for processing errors in an input/output sub-system, the method comprising:

• responsive to detecting an error, reading a value from a selected register;
• resetting the selected register;
• sending the value to an error analysis routine in which the error analysis routine identifies each bit associated with the error;
• clearing each bit identified by the error analysis routine as being associated with the error to form a cleared value;
• and
• writing the cleared value into the selected register using an OR operation such that errors occurring since the register was cleared are preserved.

A data processing system for processing errors in a hierarchical input/output sub-system having an input/output bridge with a plurality of hardware devices in a level below the bridge, the data processing system comprising:

• a bus system;
• a communications unit connected to the bus system;
• a memory connected to the bus system, wherein the memory includes a set of instructions;
• and
• a processing unit connected to the bus system, wherein the processing unit executes the set of instructions to check a register in the bridge in response to an error indication;
• scan error registers in devices in a level below the bridge in response to detecting an absence of the error in a register in the bridge;
• identify the error as an input/output error in response to a presence of an error being found by scanning the registers below the bridge;
• and identify the error as a memory error in response to an absence of an error being found by scanning the registers below the bridge.

A data processing system for processing errors in an input/output sub-system, the data processing system comprising:

• a bus system;
• a communications unit connected to the bus system;
• a memory connected to the bus system, wherein the memory includes a set of instructions;
• and
• a processing unit connected to the bus system, wherein the processing unit executes the set of instructions to read a value from a selected register to form a read value in response to detecting an error;
• reset the selected register;
• clear each bit in the read value associated with the error to form a cleared value;
• and write the cleared value into the selected register such that errors occurring since the register was cleared are preserved.

A data processing system for processing errors in an input/output sub-system, the data processing system comprising:

• a bus system;
• a communications unit connected to the bus system;
• a memory connected to the bus system, wherein the memory includes a set of instructions;
• and
• a processing unit connected to the bus system, wherein the processing unit executes the set of instructions to read a value from a selected register in response to detecting an error;
• reset the selected register;
• send the value to an error analysis routine in which the error analysis routine identifies each bit associated with the error;
• clear each bit identified by the error analysis routine as being associated with the error to form a cleared value;
• and write the cleared value into the selected register using an OR operation such that errors occurring since the register was cleared are preserved.

A data processing system for processing errors in a hierarchical input/output sub-system having an input/output bridge with a plurality of hardware devices in a level below the bridge, the data processing system comprising:

• checking means for checking a register in the bridge in response to an error indication;
• scanning means, responsive to detecting an absence of an error in the register in the bridge, for scanning error registers in devices in a level below the bridge;
• first identifying means, responsive to a presence of an error being found by scanning the registers below the bridge, for identifying the error as an input/output error;
• and
• second identifying means, responsive to an absence of an error being found by scanning the registers below the bridge, for identifying the error as a memory error.

A data processing system for processing errors in an input/output sub-system, the data processing system comprising:

• reading means, responsive to detecting an error, for reading a value from a selected register to form a read value;
• resetting means for resetting the selected register;
• clearing means for clearing each bit in the read value associated with the error to form a cleared value;
• and
• writing means for writing the cleared value into the selected register such that errors occurring since the register was cleared are preserved.

A data processing system for processing errors in an input/output sub-system, the data processing system comprising:

• reading means, responsive to detecting an error, for reading a value from a selected register;
• resetting means for resetting the selected register;
• sending means for sending the value to an error analysis routine in which the error analysis routine identifies each bit associated with the error;
• clearing means for clearing each bit identified by the error analysis routine as being associated with the error to form a cleared value;
• and
• writing means for writing the cleared value into the selected register using an OR operation such that errors occurring since the register was cleared are preserved.

A computer program product in a computer readable medium for processing errors in a hierarchical input/output sub-system having an input/output bridge with a plurality of hardware devices in a level below the bridge, the computer program product comprising:

• first instructions for checking a register in the bridge in response to an error indication;
• second instructions, responsive to detecting an absence of an error in the register in the bridge, for scanning error registers in devices in a level below the bridge;
• third instructions, responsive to a presence of an error being found by scanning the registers below the bridge, for identifying the error as an input/output error;
• and
• fourth instructions, responsive to an absence of an error being found by scanning the registers below the bridge, for identifying the error as a memory error.

A computer program product in a computer readable medium for processing errors in an input/output sub-system, the computer program product comprising:

• first instructions, responsive to detecting an error, for reading a value from a selected register to form a read value;
• second instructions for resetting the selected register;
• third instructions for clearing each bit in the read value associated with the error to form a cleared value;
• and
• fourth instructions for writing the cleared value into the selected register such that errors occurring since the registered was cleared are preserved.

A computer program product in a computer readable medium for processing errors in an input/output sub-system, the computer program product comprising:

• first instructions, responsive to detecting an error, for reading a value from a selected register;
• second instructions for resetting the selected register;
• third instructions for sending the value to an error analysis routine in which the error analysis routine identifies each bit associated with the error;
• fourth instructions for clearing each bit identified by the error analysis routine as being associated with the error to form a cleared value;
• and
• fifth instructions for writing the cleared value into the selected register using an OR operation such that errors occurring since the register was cleared are preserved.