System and methods for fault path testing through automated error injection

A fault tolerant disk array comprising:

• a controller;
• a fault injection module configured to generate fault commands;
• and
• fault logic integrated into the controller and configured to simulate faults in the fault tolerant disk array based on fault commands.

A method of validating fault tolerance in a fault tolerant system comprising:

• during a power-up process:
• generating an internal fault instruction in a fault tolerant device;
• injecting the internal fault instruction into fault logic integrated into the fault tolerant device;
• and
• based on the internal fault instruction, simulating a fault in the fault tolerant device with the fault logic.

A processor-readable medium comprising processor-executable instructions configured for:

• during a power-up process:
• generating an internal fault instruction in a fault tolerant device;
• injecting the internal fault instruction into fault logic integrated into the fault tolerant device;
• and
• based on the internal fault instruction, simulating a fault in the fault tolerant device with the fault logic.

A method of testing a fault tolerant system comprising:

• during a system power-up process,
• generating an internal fault instruction within the system;
• and
• implementing the internal fault instruction with fault logic integrated into the system;
• and
• after the system power-up process,
• receiving an external fault instruction from outside the system;
• and
• implementing the external fault instruction with the fault logic.

A processor-readable medium comprising processor-executable instructions configured for:

• during a system power-up process,
• generating an internal fault instruction within a fault tolerant system;
• and
• implementing the internal fault instruction with fault logic integrated into the fault tolerant system;
• and
• after the system power-up process,
• receiving an external fault instruction from outside the fault tolerant system;
• and
• implementing the external fault instruction with the fault logic.

A method of validating fault tolerance in a fault tolerant system comprising:

• generating a fault instruction in a test device;
• injecting the fault instruction into a fault tolerant device through an independent error injection port of the fault tolerant device;
• and
• based on the fault instruction, simulating a fault in the fault tolerant device through fault logic integrated into the fault tolerant device.