Multidispatch cpu integrated circuit having virtualized and modular resources and adjustable dispatch priority
AssigneeHewlett-Packard Development Company, L.P.
InventorsEric S. Fetzer, Wayne Kever, Eric DeLano
Life of this patent
Estimating the term…
Abstract
A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address execution pipelines and floating point execution pipelines. Each instruction decode and dispatch unit requests resources needed to perform an instruction of the resource allocation unit, which arbitrates among the multiple instruction decode and dispatch units.
Claims11
A multiple dispatch processor comprising:
- a plurality of instruction fetch units, each instruction fetch unit capable of fetching a stream of instructions;
- a plurality of instruction decode and dispatch units each coupled to a corresponding instruction fetch unit of the plurality of instruction fetch units to receive instructions therefrom;
- at least one register file coupled for storing operands;
- a plurality of execution units coupled to the register file and to the instruction decode and dispatch units for performing operations on operands as directed by the plurality of instruction decode and dispatch units;
- and
- a resource allocation unit coupled to allocate execution units among the instruction decode and dispatch units.
A resource allocation unit for a processor comprising apparatus for receiving resource requests from a plurality of instruction decode and dispatch units, and for granting a plurality of resources to the decode and dispatch units.
Dependencies are inferred from the claim text.