Method and apparatus for multi-core processor integrated circuit having functional elements configurable as core elements and as system device elements

A convertible cache memory for use in a computer system, the convertible cache having at least a cache mode and a RAM mode of operation, the cache comprising:

• a cache tag memory;
• comparison and hit logic coupled to the cache tag memory, the comparison and hit logic capable of determining cache hits in cache mode;
• a cache data memory coupled to provide data in cache mode during read operations that hit in the cache and coupled to provide data at particular addresses during read operations in RAM mode, the cache data memory being writeable at particular addresses in RAM mode;
• and
• read control circuitry for fetching cache lines to cache data memory during read operations that are determined by the comparison and hit logic to miss in the cache.

A computer system comprising:

• at least one multiple processor integrated circuit further comprising:
• a plurality of processors,
• a first and a second convertible cache capable of operating in a local memory mode and a cache mode, where the first convertible cache is associated with a first processor of the plurality of processors, and the second convertible cache is associated with a second processor of the plurality of processors, and
• at least one peripheral-specific apparatus addressable by the first processor;
• a system memory;
• wherein the first processor is capable of operating as a processor of an intelligent peripheral when the convertible cache is operated in the local memory mode, and the second processor of the plurality of processors is capable of operating as a general-purpose processor.