DMA mechanism for high-speed packet bus

A DMA (Direct Memory Access) controller device having a receive DMA engine for writing data to a memory interface, said receive DMA engine comprising:

• a write command building unit for determining which data is to be written to memory, determining first address data identifying a first memory range, the first memory range being the memory range to which the determined data is to be written, and building at least one write command to write the determined data,
• wherein the write command building unit includes a boundary alignment unit for generating second address data based on the first address data, the second address data identifying at least one second memory range that differs from the first memory range in at least one boundary, the write command building unit being arranged for building the at least one write command to write the determined data to the at least one second memory range.

A USB (Universal Serial Bus) host controller for handling the data traffic between at least one USB device and a system memory of a computer system, the USB host controller comprising a transmit and/or receive DMA (Direct Memory Access) engine, the transmit DMA engine being arranged for outputting read requests to a memory interface and receiving requested data from the memory interface, the receive DMA engine being arranged for writing data to the memory interface, said transmit and/or receive DMA engine comprising:

• an address data generating unit for generating and outputting first address data identifying a first memory range, the first memory range containing the determined data to be fetched, or being the memory range to which the determined data is to be written;
• and
• a boundary alignment unit for receiving the first address data and generating second address data therefrom, the second address data identifying at least one second memory range that differs from the first memory range in at least one boundary.