US 2003/0172215 A1Published application

Interrupt- controller

OwnerJorg Franke, Joachim Ritterinventors

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Abstract

Interrupt controller for controlling access by interrupt sources (11, 12, 13, 14) to a processor (100) and for controlling the associated branching of the current signal processing program (Rx) with a current priority (Px) in the processor. At the input end, the interrupt controller has a predetermined number of interrupt interfaces (21, 22, 23, 24) for the connection of the interrupt sources, each of the interrupt interfaces (21, 22, 23, 24) being assigned a priority value (Pi) and an address (Adi). A selection unit (30) determines from the activated interrupt interfaces the one with the highest priority value (Pmax). The through-connection of the individual interrupt interfaces (21, 22, 23, 24) to the processor (100) as an interrupt request (IR) is determined by a priority comparator (40) and a branching logic (60) which control the initiation of a context backup routine (I) in the processor (100) on the basis of the determined priority value (Pmax) and the current priority value (Px), with the branching logic determining the associated branch addresses (Vi) only toward or at the end of the currently executing context backup routine (I) so as to take into account any interrupt requests received during the context backup routine (I).

Claims6

Dependent claims

An interrupt controller for controlling access by interrupt sources (11, 12, 13, 14) to a signal input of a processor (100) and for branching a program (Rx) currently running in the processor,

the interrupt controller comprising at its input end a predetermined number of interrupt interfaces (21, 22, 23, 24) for connecting the interrupt sources thereto,
wherein each interrupt interface (21, 22, 23, 24) is assigned a, particularly programmable, priority value (Pi) and an address (Adi),
wherein a selection unit (30) selects from the interrupt interfaces activated by the interrupt sources the one with the highest priority value (Pmax) and the associated address (Adm),
wherein a priority comparator (40), based on the result of a comparison between the highest priority value (Pmax) determined by the selection unit and a current priority value (Px), generates an interrupt request signal (IR) which initiates an context backup routine (I) in the processor (100), and
wherein a branching logic (60) generates a branch address (Vi) corresponding to the highest priority value (Pmax) determined by the selection unit (30),
characterized in that
the branch address (Vi) is determined by the branching logic (60) and transferred to or callable by the processor (100) only towards the end of the context backup routine, taking into account the currently highest priority value (Pmax).

4 more elements

Dependencies are inferred from the claim text.