Data processing system with peripheral access protection and method therefor

A data processing system, comprising:

• a system bus having an address portion, a data portion, and a bus master identifier portion;
• a first bus master, coupled to the system bus;
• a second bus master, coupled to the system bus;
• a peripheral bus;
• a peripheral, coupled to the peripheral bus;
• interface circuitry for coupling the system bus to the peripheral bus;
• first storage circuit which stores a first access control value corresponding to the first bus master;
• second storage circuit which stores a second access control value corresponding to the second bus master;
• and
• bus master permission determination circuitry, coupled to the system bus and coupled to the first and second storage circuits, said bus master permission determination circuitry using the bus master identifier portion to select the first access control value in response to the bus master identifier portion indicating that a current access to the peripheral is being made by the first bus master, said bus master permission determination circuitry determining from the first access control value whether the first bus master will be denied access to the peripheral.

A method for providing peripheral access protection in a data processing system, comprising:

• providing a first bus master;
• providing a second bus master;
• initiating a first bus cycle which requires access to a peripheral;
• providing a first bus master identifier which corresponds to the first bus master during at least a portion of the first bus cycle;
• using the first bus master identifier to select first access control information for the first bus cycle;
• using the first access control information to determine if the first bus cycle will be terminated because the first bus master is not allowed access to the peripheral;
• initiating a second bus cycle which requires access to the peripheral;
• providing a second bus master identifier which corresponds to the second bus master during at least a portion of the second bus cycle;
• using the second bus master identifier to select second access control information for the second bus cycle;
• and
• using the second access control information to determine if the second bus cycle will be terminated because the second bus master is not allowed access to the peripheral.