Calculating a sum of numbers using an overflow counter in an environment exceeded by the numbers in bit-size

A method for calculating a sum of numbers using an overflow counter in an environment exceeded by the numbers in bit-size, the method comprising:

• accessing a least significant portion of a first number of a plurality of numbers;
• accessing a least significant portion of a second number of the plurality of numbers;
• adding the least significant portion of the first number to the least significant portion of the second number, the resulting sum comprising a first intermediate number;
• if a carry is generated by the addition of the least significant portion of the first number to the least significant portion of the second number, incrementing an overflow counter to record the generated carry;
• accessing each of a plurality of least significant portions of the remaining plurality of numbers, adding each of the plurality of least significant portions to the first intermediate number, and incrementing the overflow counter each time a carry is generated to record the generated carry;
• after each of the plurality of least significant portions has been added to the first intermediate number, storing the first intermediate number, the first intermediate number comprising a least significant portion of the sum of the plurality of numbers;
• accessing a most significant portion of the first number;
• adding the overflow counter to the most significant portion of the first number, the resulting sum comprising a second intermediate number;
• accessing each of a plurality of most significant portions of the remaining plurality of numbers and adding each of the plurality of most significant portions to the second intermediate number;
• and
• after each of the plurality of most significant portions has been added to the second intermediate number, storing the second intermediate number, the second intermediate number comprising a most significant portion of the sum of the plurality of numbers.

Logic for calculating a sum of 64-bit numbers using an overflow counter in a 32-bit environment, the logic encoded in a digital signal processor (DSP) and when executed operable to:

• access a least significant 32-bit portion of a first 64-bit number of a plurality of 64-bit numbers, each of the plurality of 64-bit numbers stored in two memory locations within data memory for the DSP;
• access a least significant 32-bit portion of a second 64-bit number of the plurality of 64-bit numbers;
• add the least significant 32-bit portion of the first 64-bit number to the least significant portion of the second 64-bit number, the resulting sum comprising a first intermediate 32-bit number;
• if a carry is generated by the addition of the least significant 32-bit portion of the first 64-bit number to the least significant 32-bit portion of the second 64-bit number, increment an overflow counter to record the generated carry, the overflow counter stored in a status register of the DSP;
• access each of a plurality of least significant 32-bit portions of the remaining plurality of 64-bit numbers, add each of the plurality of least significant 32-bit portions to the first intermediate 32-bit number, and increment the overflow counter each time a carry is generated to record the generated carry;
• after each of the plurality of least significant 32-bit portions has been added to the first intermediate 32-bit number, store the first intermediate 32-bit number, the first intermediate 32-bit number comprising a least significant 32-bit portion of the sum of the plurality of 64-bit numbers;
• access a most significant 32-bit portion of the first 64-bit number;
• add the overflow counter to the most significant 32-bit portion of the first 64-bit number, the resulting sum comprising a second intermediate 32-bit number;
• access each of a plurality of most significant 32-bit portions of the remaining plurality of 64-bit numbers and add each of the plurality of most significant 32-bit portions to the second intermediate 32-bit number;
• and
• after each of the plurality of most significant 32-bit portions has been added to the second intermediate 32-bit number, store the second intermediate 32-bit number, the second intermediate 32-bit number comprising a most significant 32-bit portion of the sum of the plurality of 64-bit numbers.

A method for calculating a sum of 64-bit numbers using an overflow counter in a 32-bit environment, the method executed by a digital signal processor (DSP) and comprising:

• accessing a least significant 32-bit portion of a first 64-bit number of a plurality of 64-bit numbers, each of the plurality of 64-bit numbers stored in two memory locations within data memory for the DSP;
• accessing a least significant 32-bit portion of a second 64-bit number of the plurality of 64-bit numbers;
• adding the least significant 32-bit portion of the first 64-bit number to the least significant portion of the second 64-bit number, the resulting sum comprising a first intermediate 32-bit number;
• if a carry is generated by the addition of the least significant 32-bit portion of the first 64-bit number to the least significant 32-bit portion of the second 64-bit number, incrementing an overflow counter to record the generated carry, the overflow counter stored in a status register of the DSP;
• accessing each of a plurality of least significant 32-bit portions of the remaining plurality of 64-bit numbers, adding each of the plurality of least significant 32-bit portions to the first intermediate 32-bit number, and incrementing the overflow counter each time a carry is generated to record the generated carry,
• after each of the plurality of least significant 32-bit portions has been added to the first intermediate 32-bit number, storing the first intermediate 32-bit number, the first intermediate 32-bit number comprising a least significant 32-bit portion of the sum of the plurality of 64-bit numbers;
• accessing a most significant 32-bit portion of the first 64-bit number;
• adding the overflow counter to the most significant 32-bit portion of the first 64-bit number, the resulting sum comprising a second intermediate 32-bit number;
• accessing each of a plurality of most significant 32-bit portions of the remaining plurality of 64-bit numbers and adding each of the plurality of most significant 32-bit portions to the second intermediate 32-bit number;
• and
• after each of the plurality of most significant 32-bit portions has been added to the second intermediate 32-bit number, storing the second intermediate 32-bit number, the second intermediate 32-bit number comprising a most significant 32-bit portion of the sum of the plurality of 64-bit numbers.