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AssigneeQuickturn Design Systems, Inc.
InventorsWilliam John Schilp, Pramodini Arramreddy, Krishna Babu Bangera, Makarand Yashwant Joshi
Estimating the term…
A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.
A simulator for a design under test, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
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Circuit design at the digital level: design verification, e.g. functional simulation or model checking
Computing and data processing
Term end not estimated
This invention relates to electronic systems, and more particularly to systems and methods for performing accelerated hardware simulation of electronic system designs.
Modern electronic systems are frequently implemented as a combined hardware/software system built on a single silicon chip. In order to ensure that these chips will function properly, it is useful to test the full-system design of the electronic system, before incurring the expenses of actually creating the physical silicon chips. The full-system designs are typically tested by implementing the design in a simulator, and then running a simulated operation of the design. With the ability to mix processors, complex peripherals and custom hardware and software on a single chip, full-system design and analysis places an ever increasing demand on the simulators, to speed up the simulation process.
Conventional hardware accelerated simulators are composed of a hardware accelerator box, which contains the hardware components used to implement the design-under-test (DUT), and a host workstation which is used to control the simulated operation of the DUT. The host workstation has a variety of software routines used to interface with the hardware accelerator box and perform other desired functions in the simulation process. For example, the host workstation provides all of the various design clock signals used to provide timing for the various elements of the DUT. In the DUT, events only occur when one of the design clocks changes state, referred to as a design clock “edge”. The host workstation may also contain software implemented models of certain portions of the full-system design, such as C-models, which are software models of particular circuits, written in a high-level language such as the C programming language. These software models interact with the hardware DUT as desired by the system designer.
The accompanying drawings are included to provide a further understanding of embodiments of the invention and together with the Detailed Description, serve to explain the principles of the embodiments disclosed.
FIG. 1 shows a simulator according to an embodiment of the invention.
FIG. 2 shows a simulation control module according to an embodiment of the invention.
Turning to FIG. 1, a simulator 100 in accordance with an embodiment of the invention includes a host workstation 105 and a hardware accelerator box 110. The host workstation 105 is a computer adapted to operate software used in interfacing with, controlling, and responding to the various systems with the hardware accelerator box 110.
The hardware accelerator box 110 is the hardware platform onto which the hardware portion of a full-system design is configured for simulation. The hardware accelerator box 110 is composed of a collection of programmable devices such as programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), or other similar devices. These devices are adapted to be configured by the host workstation 105, such that the devices embody the hardware portion of a full-system design, such as the design-under-test (DUT) 130. These devices additionally are adapted to be configured by the host workstation 105 to embody any desired circuitry, such as the simulation control module (SCM) 135, used to interface between the host workstation 105 and the DUT 130.
The host workstation 105 contains a user interface 115, a software clock facility 120, a simulation control module layer 123, and a collection of C-models 125. The user interface 115 is a software module adapted to provide an interface between a user such as a design or test engineer and the simulator 10. The user interface 115 accepts inputs from the user, manipulates these inputs as desired by the design parameters provided by the user or from other sources, provides data, control signals, commands and the like to the hardware accelerator box 110, accepts outputs from the hardware accelerator box 110, manipulates these outputs as desired by the design parameters specified by the user or others, and provides the outputs to the user. The user interface 115 also interfaces with the software clock facility 120, the SCM layer 123, the collection of C-models 125, and any other components of the simulator 100, as desired by the user.