Method for transforming stand-alone verification tests for an embedded block into serial scan test patterns for detecting manufacturing defects

A method of transforming a stand-alone verification test for a functional block into a serial scan test pattern for detecting manufacturing defects, comprising:

• designing a functional block based on a set of design considerations;
• generating a parallel functional pattern for testing the functional block;
• and
• translating the parallel functional pattern into a serial pattern;
• compiling information for use in software translation of the parallel functional pattern into a serial pattern.

An apparatus for transforming a stand-alone verification test for a functional block into a serial scan test pattern for detecting manufacturing defects, comprising:

• a functional block designed based on a set of design considerations and comprising a scan boundary,
• the scan boundary comprising a scan in chain and a scan out chain,
• a parallel functional pattern for testing the functional block;
• and
• software for translating the parallel functional pattern into a serial pattern that is fed into the scan in chain, evaluated, and fed out of the scan out chain.