Optimized wireless LAN solution for embedded systems

Abstract

An improved WLAN solution for embedded systems incorporating optimized partitioning; it reduces power consumption and systems cost by up to 50%. All silicon gates associated with the redundant RISC processor, redundant SRAM and flash memories used in prior art WLAN solutions are eliminated. The invention includes a low gate count PHY Accelerator ASIC, a dual core processor (DCP), a portion of the PHY in software, and an innovative software MAC architecture supported by minimal hardware acceleration. The DCP is a standard off-the-shelf component incorporating DSP and RISC processors. It executes software portions of the MAC and PHY. The DCP communicates with the PHY Accelerator through a novel parallel interface that improves throughput while reducing processing requirements on DCP. Also, the PHY accelerator, or certain portions of it, may be embedded into the DCP. Invention includes a novel “resource utilization scheme”, whereby the various DCP resources get judiciously re-deployed.

Dependencies are inferred from the claim text.