Planarizing method for fabricating gate electrodes

A method for fabricating a semiconductor integrated circuit microelectronic fabrication comprising:

• providing a semiconductor substrate having defined therein a first active region of a first polarity laterally adjacent a second active region of a second polarity opposite the first polarity;
• forming over the first active region but not over the second active region a patterned first gate electrode material layer of the second polarity, the patterned first gate electrode material layer having formed aligned thereupon a first planarizing stop layer;
• forming over the first planarizing stop layer and the second active region a blanket second gate electrode material layer of the first polarity;
• planarizing, while employing a planarizing method in conjunction with the planarizing stop layer, the blanket second gate electrode material layer to form therefrom a patterned second gate electrode material layer laterally adjacent but not over the patterned first gate electrode material layer;
• and
• further patterning the patterned first gate electrode material layer and the patterned second gate electrode material layer to form a corresponding first gate electrode over the first active region and a corresponding second gate electrode over the second active region.