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US 2003/0170970 A1Published application
Semiconductor device and method of manufacturing the same
OwnerKouji Senoo, Hiroyuki Nagaiinventors
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OwnerKouji Senoo, Hiroyuki Nagaiinventors
Estimating the term…
A semiconductor device having reduced interconnect delay and increased interconnect reliability and a method of manufacturing the same are provided. A plurality of interconnects 12a through 12f are formed on a base insulating layer 10 with different interconnect pitches P1 through P3. Next, an adhesion inhibiting layer inhibiting adhesion to an interlayer insulating layer 16 formed on the interconnects is formed in the space between adjacent interconnects of a smaller interconnect pitch in which space the interconnect delay is predicted to exceed a predetermined value due to interconnect design. In a formed semiconductor device 18, gaps of a small dielectric constant are formed in the spaces between interconnects of the smaller interconnect pitches (parts C), while an insulating film is buried selectively in the spaces between interconnects of the larger interconnect pitches (parts A and B).
(Amended) A semiconductor device formed by forming an insulating layer on a base insulating layer on which at least two or more interconnects are formed to project therefrom, characterized in that:
A method of manufacturing a semiconductor device, the method including an interconnect forming step of forming at least two or more interconnects on a substrate so that the interconnects project therefrom and an interlayer insulating layer forming step of forming an interlayer insulating layer, characterized by including:
A method of manufacturing a semiconductor device, the method including an interconnect forming step of forming at least two or more interconnects on a substrate so that the interconnects project therefrom and an interlayer insulating layer forming step of forming an interlayer insulating layer, characterized in that:
Dependencies are inferred from the claim text.