US 2003/0170957 A1Published application

Novel self aligned channel implant, elevated S/D process by gate electrode damascene

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChu-Wei Hu, Jiue-Wen Weng, Chung-Te Lin, So Wein Kuo

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Abstract

A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

Claims28

Dependent claims

A method of forming a semiconductor for use with a gate electrode damascene process, comprising:

providing a semiconductor silicon substrate;
forming a thin dielectric layer on top of said substrate;
depositing a thick layer of oxide on top of said thin dielectric layer;
creating a pattern said pattern to penetrate and go through said thick layer of oxide furthermore to penetrate and go through said thin dielectric layer furthermore to penetrate the surface of said silicon substrate;
forming a thin layer of oxide at the bottom of said pattern;
performing a channel implant in said silicon substrate said implant to be self-aligned with said pattern said channel implant to penetrate said substrate to a depth between 0.02 and 1.5 um;
forming Lightly Doper Drain areas in said silicon substrate said LDD areas to be self-aligned with the extreme corners of said bottom of said pattern;
forming a pocket implant in said silicon substrate said pocket implant to be self-aligned with said pattern;
forming a spacer on the sidewalls of said pattern, removing said thin layer of oxide from the bottom of said pattern where said thin layer of oxide is not covered by said spacer;
forming a gate dielectric at, the bottom of said pattern where said thin layer of oxide has been removed;
forming a gate electrode in said pattern;
removing said thick layer of oxide from the top of said thin dielectric layer;
removing said thin dielectric layer from the top of said substrate;
and
performing source and drain implant in the surface of said silicon substrate said implant to be substantially self-aligned with said with said pattern.

12 more elements

A method of forming a semiconductor for use with a gate electrode damascene process, comprising:

providing a semiconductor silicon substrate;
forming a thin dielectric layer on top of said substrate;
depositing a thick layer of oxide on top of said thin dielectric layer;
creating a pattern said pattern to penetrate and go through said thick layer of oxide furthermore to penetrate and go through said thin dielectric layer furthermore to penetrate the surface of said silicon substrate;
forming a thin layer of oxide at the bottom of said pattern;
forming a spacer on the sidewalls of said pattern;
performing a channel implant in said silicon substrate said implant to be self-aligned with said pattern wherein said channel implant penetrates the surface of said substrate to a depth within the range of between 0.02 and 1.5 um;
removing said thin layer of oxide from the bottom of said pattern where said thin layer of oxide is not covered by said spacer;
forming a gate dielectric at the bottom of said pattern where said thin layer of oxide has been removed;
forming a gate electrode in said pattern;
removing said thick layer of oxide from the top of said thin dielectric layer;
removing said thin dielectric layer from the top of said substrate;
performing source and drain implant in the surface of said silicon substrate said implant to be substantially self-aligned with said pattern;
forming salicide on the surface of said silicon substrate above said source and drain implants and on the top surface of said gate electrode;
removing said spacer from the sidewalls of said pattern;
and
forming Lightly Doper Drain areas in said silicon substrate said LDD areas to be self-aligned with the extreme corners of said bottom of said pattern.

14 more elements

A method of forming a semiconductor for use with a gate electrode damascene process, comprising:

providing a semiconductor silicon substrate;
forming a thin dielectric layer on top of said substrate;
depositing a thick layer of oxide on top of said thin dielectric layer;
creating a pattern said pattern to penetrate and go through said thick layer of oxide furthermore to penetrate and go through said thin dielectric layer furthermore to penetrate the surface of said silicon substrate said penetration of said substrate to be to considerable depth;
forming a thin layer of oxide at the bottom of said pattern;
performing a channel implant in said silicon substrate said implant to be self-aligned with said pattern;
forming a spacer on the sidewalls of said pattern;
removing said thin layer of oxide from the bottom of said pattern where said thin layer of oxide is not covered by said spacer;
forming a gate dielectric at the bottom of said pattern where said thin layer of oxide has been removed;
forming a gate electrode in said pattern;
removing said thick layer of oxide from the top of said thin dielectric layer;
removing said thin dielectric layer from the top of said substrate;
performing source and drain implant in the surface of said silicon substrate said implant to be substantially self-aligned with said with said pattern;
and
forming silicide on the surface of said silicon substrate above said source and drain implants and on the top surface of said gate electrode.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/385,954Filed 11 Mar 2003
Priority: 10 Aug 2001
Published: 11 Sep 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 30/022
Of FETs having insulated gates [IGFET]: having lightly-doped source or drain extensions selectively formed at the sides of the gates
H10D 30/0217
Of FETs having insulated gates [IGFET]: forming self-aligned punch-through stoppers or threshold implants under gate regions
H10D 30/608
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having non-planar bodies, e.g. having recessed gate electrodes
H10D 64/015
Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers

Family

Application09/927,073Continuation · filed 10 Aug 2001
Application10/385,954Continuation · filed 11 Mar 2003
US 2002/0182815 A1Published application
US 6,790,756 B2Related patent
US 2003/0170957 A1This patent

From the US filing history. Foreign family members aren’t listed.