Ultra-thin gate oxide through post decoupled plasma nitridation anneal
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsDong Zhong, Yun Ling Tan, Chew Hoe Ang, Jia Zhen Zheng
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Abstract
DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050° C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.
Claims15
A process for improving the integrity of a layer of silicon oxide having an upper surface, comprising:
- on a substrate, providing said layer of silicon oxide;
- by means of decoupled plasma nitridation, forming a nitrogen bearing layer that extends downwards a distance from said upper surface;
- and
- then annealing said nitrogen bearing layer in a mixture of nitrogen and oxygen, at a temperature between about 1,000 and 1,100° C. and a pressure between about 5 and 15 torr, for between about 60 and 150 minutes, whereby said nitrogen bearing layer becomes substantially free of structural defects.
A process for forming a field effect transistor, comprising:
- providing a silicon wafer, of a first conductivity type, and forming thereon a layer of silicon oxide having an upper surface;
- by means of decoupled plasma nitridation, forming a nitrogen bearing layer that extends downwards a distance from said upper surface;
- then annealing said nitrogen bearing layer in a mixture of nitrogen and oxygen, at a temperature between about 1,000 and 1,100° C. and a pressure between about 5 and 15 torr, for between about 60 and 150 minutes, whereby said nitrogen bearing layer becomes substantially free of structural defects;
- depositing a layer of polysilicon on said layer of silicon oxide;
- patterning and etching said layer of polysilicon and said layer of silicon oxide to form a gate pedestal on a layer of gate oxide;
- and
- using said gate pedestal as a mask, forming source and drain regions of a second conductivity type that immediately abut said gate oxide, thereby forming said field effect transistor and whereby said field effect transistor has an electrical performance as good as a device that is similar in all respects to said field effect transistor except for the absence of said nitrogen bearing layer.
Dependencies are inferred from the claim text.