Advanced metallization approach for forming self-aligned contacts and local area interconnects for memory and logic devices

A method of fabricating a memory circuit on a semiconductor substrate, wherein in the substrate includes an array of memory cells arranged in rows/columns, and wherein each of the memory cells includes a stacked gate, a source, and a drain, wherein each source and drain in the array includes corresponding source and drain junctions, comprising:

• forming discrete and similarly sized self-aligned source and drain contacts in a first layer disposed over the array to each of the source and drain junctions, respectively, in the array;
• forming self-aligned local area slotted vias in a second layer disposed over the first layer to form local area interconnects, wherein each of the formed local area interconnects electrically shunt all of the source junctions through the formed source contacts in each of the rows in the array, and further forming discrete self-aligned drain extensions over each of the formed self-aligned drain contacts to electrically connect the drain junctions to the extensions;
• and
• plugging and filling substantially simultaneously each of the formed self-aligned contacts, drain extensions, and slotted vias with a conductive material to form the array including self-aligned drain contacts and slotted local area interconnects that electrically shunt all of the source junctions.

A method of fabricating a logic circuit including an array of memory cells, wherein in the memory cells in the array are arranged in rows/columns, and wherein each of the memory cells includes a stacked gate, a source, and a drain, wherein each source and drain in the array includes corresponding source and drain junctions, comprising:

• forming discrete and similarly sized self-aligned source and drain contacts in a first layer disposed over the array to each of the source and drain junctions, respectively, in the array;
• forming self-aligned local area slotted vias in a second layer disposed over the first layer to form local area interconnects, wherein each of the formed local area interconnects electrically shunt all of the source junctions to the cells in each of the rows in the array, and further forming discrete self-aligned drain extensions over each of the formed self-aligned drain contacts to electrically connect the drain junctions to the extensions;
• and
• plugging and filling in a single step each of the formed self-aligned contacts, drain extensions, and slotted vias with a conductive material to form the array including self-aligned drain contacts and the slotted local area interconnects that electrically shunt all of the source junctions.

An integrated memory circuit device, comprising:

• an array of memory cells, wherein each of the memory cells includes a stacked gate, a source, and a drain, wherein the array further includes source and drain junctions coupled to each source and drain, respectively, in the array;
• internal circuitry;
• a first layer including discrete and self-aligned source and drain metal contacts, wherein each of the drain contacts electrically couple to each of the drain junctions in the array;
• and
• a second layer disposed over the first layer, wherein the second layer includes self-aligned local area interconnects, wherein each of the local area interconnects electrically shunt all of the source junctions through the formed source contacts in each row in the array to form the integrated memory circuit device.

A logic circuit, comprising:

• an array of memory cells, wherein each of the memory cells includes a stacked gate, a source, and a drain, wherein the array further includes source and drain junctions coupled to each source and drain, respectively, in the array;
• internal logic circuitry;
• discrete and self-aligned source and drain metal contacts, wherein each of the drain contacts electrically couple to each of the drain junctions in the array;
• and
• self-aligned local area interconnects that electrically shunt all of the source junctions through the source contacts in each row in the array to form the array.