Method for low topography semiconductor device formation
AssigneeInternational Business Machines Corporation
InventorsDavid B. Colavito, Nivo Rovedo, Phung T. Nguyen
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Abstract
A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.
Claims11
A method for forming a planarized field effect transistor (FET), the method comprising:
- defining an active semiconductor region upon a substrate, said active semiconductor region further comprising a pair of mesa regions therein;
- defining a source region within a top surface of one of said pair of mesa regions;
- defining a drain region within a top surface of the other of said pair of mesa regions;
- depositing a gate material between said pair of mesa regions;
- and
- planarizing said gate material, thereby forming a gate;
- wherein a top surface of said gate is substantially planar with said source and drain regions.
Dependencies are inferred from the claim text.